Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations

A memory device, comprising:

• a plurality of word lines and a plurality of bit lines, wherein the plurality of bit lines comprises a plurality of local bit lines, each electrically connected to a corresponding one of a plurality of global bit lines by respective corresponding one of a plurality of gain stage transistors, the plurality of gain stage transistors having transistor parameters that vary with at least one of process, voltage, and temperature;
• a plurality of two-terminal memory elements, each two-terminal memory element coupled between a respective word line of the plurality of word lines and a respective bit line of the plurality of bit lines;
• a controller coupled to the plurality of gain stage transistors, the controller configured to:
• precharge a first selected local bit line of the plurality of bit lines to a first voltage that varies with the transistor parameters of the corresponding gain stage transistor;
• and
• after precharging the first selected local bit line, applying a voltage to a selected word line of the cross point memory array to read the memory element coupled between the first selected local bit line and the selected word line.