Back to results
US 9,112,529 B1Granted
Method and system for forward error correction of interleaved-formated data
AssigneeXilinx, Inc.
InventorsRaied N. Mazahreh, Raghavendar M. Rao
Life of this patent
Estimating the term…
Abstract
In one embodiment, a device is provided. The device includes a first formatting circuit configured to add zero padding bits to a received data block. An FEC encoder circuit is coupled to the first formatting circuit and is configured to determine parity bits for the data block at a first code rate. A second formatting circuit is coupled to the FEC encoder circuit and is configured to combine the parity bits with the data block and remove the zero padding bits to provide an FEC coded data block at a second code rate. The second code rate is less than the first code rate.
Claims19
A device, comprising:
- a first formatting circuit configured to add zero padding bits to a received data block;
- a forward error correction (FEC) encoder circuit coupled to the first formatting circuit and configured to determine parity bits for the data block at a first code rate;
- and
- a second formatting circuit coupled to the FEC encoder circuit and configured to combine the parity bits with the data block and remove the zero padding bits to provide an FEC coded data block at a second code rate, the second code rate being less than the first code rate;
- wherein the first formatting circuit includes:
- a row de-interleaver circuit configured to format the received data block into a row-aligned format, wherein each row of the data block in the row-aligned format includes data bits equal to data bits in a corresponding row in a de-interleaved format;
- and
- a column de-interleaver circuit configured to format the received data block into a column-aligned format, wherein each row of the data block in the column-aligned format includes data bits equal to data bits in a corresponding column in the de-interleaved format;
- the FEC encoder circuit includes:
- a row encoding circuit coupled to the first formatting circuit and configured to perform FEC coding on the rows of the data block in the row-aligned format to produce a row-coded data block;
- and
- a column encoding circuit coupled to the second formatting circuit and configured to perform FEC coding on rows of the data block in the column-aligned format, the rows corresponding to respective columns of the data block in the de-interleaved format, to produce a column-coded data block;
- and
- the second formatting circuit is configured to combine the row-coded data block and the column-coded data block to produce an FEC coded data block and remove the zero padding bits.
11 more elements
A circuit for forward error correction decoding, comprising:
- a decoding pipeline including a plurality of decoding stages, each decoding stage configured to receive blocks of data symbols and FEC datagrams in an interleaved format, each of a first set of the FEC datagrams corresponding to a respective row of the data symbols in a de-interleaved format and each of a second set of the FEC datagrams corresponding to a respective column of the data symbols in the de-interleaved format, each decoding stage including:
- a first formatting circuit configured to format the data symbols in the interleaved format into a row-aligned format, wherein each row of the data symbols in the row-aligned format includes symbols equal to symbols in a corresponding row in the de-interleaved format;
- a row decoding circuit coupled to the first formatting circuit and configured to perform FEC decoding of the data symbols in the row-aligned format using the first set of FEC datagrams;
- a second formatting circuit coupled to the row decoding circuit and configured to format the data symbols in the row-aligned format into a column-aligned format, wherein each row of the data symbols in the column-aligned format includes symbols equal to symbols in a corresponding column in the de-interleaved format;
- a column decoding circuit coupled to the second formatting circuit and configured to perform FEC decoding of the data symbols in the column-aligned format using the second set of FEC datagrams;
- and
- a third formatting circuit coupled to the column decoding circuit and configured to format the data symbols in the column-aligned format into the interleaved format.
4 more elements
A method for forward error correction (FEC) encoding, comprising:
- receiving a first plurality of data symbols;
- adding a second plurality of symbols including zero padding bits to the first plurality of data symbols to form a data block;
- formatting the data block into a de-interleaved format;
- determining a first set of FEC datagrams including a respective datagram for each row of symbols of the data block in the de-interleaved format;
- determining a second set of FEC datagrams including a respective datagram for each column of symbols of the data block in the de-interleaved format;
- adding the first and second sets of FEC datagrams to the data block in the de-interleaved format to produce an FEC coded data block;
- removing the second plurality of symbols including the zero padding bits from the FEC coded data block to produce a reduced size FEC coded data block;
- and
- formatting the reduced size FEC coded data block into an interleaved format.
6 more elements
Dependencies are inferred from the claim text.