Contact structure of semiconductor device

A metal oxide semiconductor field effect transistor (MOSFET) comprising:

• a substrate comprising a major surface;
• a gate stack on the major surface of the substrate;
• a trench below the major surface adjacent to the gate stack;
• a shallow trench isolations (STI) region disposed on a side of the trench opposite the gate stack, wherein the STI region is within the substrate;
• a semiconductive strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate;
• an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a bottom comprising the semiconductive strained material;
• a metal oxide layer coating the sidewalls and bottom of the opening, wherein the metal oxide layer has a thickness ranging from 1 nm to 10 nm;
• and
• a metal layer filling a coated opening of the dielectric layer.

A contact structure for a semiconductor device comprising:

• a silicon substrate comprising a major surface and a trench below the major surface;
• a strained material comprising germanium filling the trench, the strained material having a topmost surface and a bottommost surface and being of substantially uniform composition from the topmost surface to the bottommost surface;
• an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a bottom comprising the topmost surface of the strained material;
• a metal oxide layer coating the sidewalls and bottom of the opening, wherein the metal oxide layer has a thickness ranging from 1 nm to 10 nm;
• and
• a metal layer filling a coated opening of the metal oxide layer.