Find-first-set bit circuit and method

A find-first-set circuit, comprising:

• a translator circuit having an input port coupled to receive an n-bit input word, wherein n>1, and the translator circuit is configured to generate n n-bit patterns, each pattern corresponding to one bit position of the n-bit input word:
• wherein in response to the one bit position of the n-bit input word having a logic 1 value, the translator circuit is configured to generate the corresponding pattern having a logic 1 value in a corresponding bit position of the n-bit pattern, a logic 1 value in each bit position left of the corresponding bit position of the n-bit pattern, and a logic 0 value in each bit position right of the corresponding bit position of the n-bit pattern;
• wherein in response to the one bit position of the n-bit input word having a logic 0 value, the translator circuit is configured to generate the corresponding pattern having a logic 0 value in each bit position of the n-bit pattern;
• a merge circuit coupled to receive the n n-bit patterns and configured to combine the n n-bit patterns into one merged n-bit pattern;
• and
• an indicator circuit coupled to receive the merged n-bit pattern and configured to generate an output n-bit pattern having a logic 1 value in one bit position and a logic 0 value in every other bit position, the one bit position equal to a rightmost bit position of the n-bit input word having a logic 1 value.

A find-first-set circuit, comprising:

• a plurality of first detector circuits;
• wherein each first detector circuit is configured to receive respective first n-bit input words, wherein n>1 and each respective first n-bit input word is a portion of an m-bit input word;
• wherein each first detector circuit is further configured to generate a respective first output n-bit pattern having a logic 1 value in one bit position and a logic 0 value in every other bit position, the one bit position equal to a rightmost bit position of the respective first n-bit input word having a logic 1 value;
• a reduction circuit coupled to receive the respective first output n-bit patterns;
• wherein the reduction circuit is configured to reduce each respective first output n-bit pattern to a respective output bit having a logic value that indicates whether or not any bit of the respective first output n-bit pattern has a logic value 1;
• a second detector circuit coupled to receive the respective output bits from the reduction circuit as an m/n-bit input word;
• wherein the second detector circuit is configured to generate an output m/n-bit pattern having a logic 1 value in one bit position and a logic 0 value in every other bit position, the one bit position equal to a rightmost bit position of the m/n-bit input word having a logic 1 value;
• and
• a mask circuit coupled to receive the respective first output n-bit patterns and the output m/n-bit pattern;
• wherein the mask circuit is configured to generate an output m-bit pattern having a logic 1 value in one bit position and a logic 0 value in every other bit position, the one bit position equal to a rightmost bit position of the m-bit input word having a logic 1 value.