Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating
AssigneeZeno Semiconductor, Inc.
InventorYuniarto Widjaja
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Abstract
Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.
Claims12
A semiconductor memory cell comprising:
- a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell;
- and
- a non-volatile memory comprising a resistance change element configured to receive transfer of data stored in said floating body under any one of a plurality of predetermined conditions;
- wherein said capacitorless transistor and said non-volatile memory are connected in series;
- wherein current flowing to said resistance change element flows through said floating body;
- wherein one of said predetermined conditions comprises loss of power to said cell;
- wherein said cell is configured to perform a shadowing process when said data in said floating body is loaded into and stored in said nonvolatile memory;
- wherein, upon restoration of power to said cell, said data in said nonvolatile memory is loaded into said floating body and stored therein;
- and
- wherein said cell is configured to reset said nonvolatile memory to an initial state after loading said data into said floating body upon said restoration of power.
A semiconductor memory cell comprising:
- a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell;
- and
- a non-volatile memory comprising a resistance change element configured to receive transfer of data stored in said floating body under any one of a plurality of predetermined conditions;
- wherein said capacitorless transistor and said non-volatile memory are connected in series;
- wherein one of said predetermined conditions comprises loss of power to said cell, wherein said cell is configured to perform a shadowing process wherein said data in said floating body is loaded into and stored in said nonvolatile memory;
- wherein, upon restoration of power to said cell, said data in said nonvolatile memory is loaded into said floating body and stored therein;
- and
- wherein said cell is configured to reset said nonvolatile memory to an initial state after loading said data into said floating body upon said restoration of power.
A semiconductor memory cell comprising:
- a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell;
- and
- a non-volatile memory comprising a resistance change element configured to receive transfer of data stored in said floating body upon unintentional power loss or intentional power loss to said cell;
- wherein said capacitorless transistor and said non-volatile memory are connected in series;
- wherein said cell is configured to perform a shadowing process wherein said data in said floating body is loaded into and stored in said nonvolatile memory;
- wherein, upon restoration of power to said cell, said data in said nonvolatile memory is loaded into said floating body and stored therein;
- and
- wherein said cell is configured to reset said nonvolatile memory to an initial state after loading said data into said floating body upon said restoration of power.
Dependencies are inferred from the claim text.