System and method for a cache in a multi-core processor

A cache system for multi-core processors, comprising:

• a plurality of processor cores;
• and
• a closely coupled LEVEL-1 data cache coupled to each of the processor cores, wherein the LEVEL-1 caches include memory for caching data and are physically interconnected by a tree communication structure,
• the tree communication structure having at least two levels, wherein
• a first level of the two levels comprises the LEVEL-1 caches, and
• a second level of the two levels comprises at least one higher level cache having a higher level than the LEVEL-1 caches and including memory for caching data,
• wherein each of a plurality of addresses is cached only once within all LEVEL-1 caches of the processor cores,
• at least some processor cores have access to the LEVEL-1 cache of at least one other processor core for transmitting data, and
• a plurality of the LEVEL-1 caches having an extended cache tag structure for storing a reference between an address and at least one other of the LEVEL-1 caches having the data of the respective address cached, wherein each of the extended cache tag structures is physically located in a respective one of the LEVEL-1 caches.

A cache system for multi-core processors, comprising:

• a plurality of processor cores;
• and
• a closely coupled LEVEL-1 data cache coupled to each of the processor cores, wherein the LEVEL-1 caches include memory for caching data and are physically interconnected by a tree communication structure,
• the tree communication structure having at least two levels, wherein
• a first level of the two levels comprises the LEVEL-1 caches, and
• a second level of the two levels comprises at least one higher level cache having a higher level than the LEVEL-1 caches and including memory for caching data,
• wherein a plurality of memories for storing TAG information are associated to the memories for caching data of the LEVEL-1 caches, the TAG information referencing the data, wherein each of the memories for storing TAG information is physically located in a respective one of the LEVEL-1 caches,
• wherein each of a plurality of addresses is cached only once within all LEVEL-1 caches of the processor cores, and
• wherein each processor core is operative to request an address and cause a movement of a cache line related to an address from the LEVEL-1 cache of a processor core owning the cache line into the LEVEL-1 cache of the processor core requesting the address.

A method for operating LEVEL-1 caches in a multi-core processor, the method comprising:

• caching an address only once within all of a plurality of LEVEL-1 caches of the processor, wherein each of the LEVEL-1 caches includes memory for caching data and is closely coupled to a processor core, and wherein the LEVEL-1 caches are physically interconnected by a tree communication structure,
• the tree communication structure having at least two levels, wherein
• a first level of the two levels comprises the LEVEL-1 caches, and
• a second level of the two levels comprises at least one higher level cache having a higher level than the LEVEL-1 caches and including memory for caching data, and
• wherein a plurality of memories for storing TAG information are associated to the memories for caching data of the LEVEL-1 caches, the TAG information referencing the data, wherein each of the memories for storing TAG information is physically located in a respective one of the LEVEL-1 caches;
• and
• moving a cache line related to an address from the LEVEL-1 cache of a processor core owning the cache line into the LEVEL-1 cache of a processor core requesting the address.

A single package multi-core processor comprising:

• at least four processor cores, each processor core having a local LEVEL-1 cache including memory for caching data,
• a tree communication structure physically interconnecting the multiple LEVEL-1 caches,
• the tree communication structure having a plurality of nodes, wherein the processor cores with the respective local caches are leaf nodes of the tree communication structure and a LEVEL-2 cache is a root node of the tree communication structure, the LEVEL-2 cache including memory for caching data,
• wherein a plurality of memories for storing TAG information are associated to the memories for caching data of the LEVEL-1 caches, the TAG information referencing the data, wherein each of the memories for storing TAG information is physically located in a respective one of the LEVEL-1 caches, and
• wherein at least some edges between the nodes comprise a plurality of buses being operative to handle multiple accesses or transfers in parallel.

A single package multi-core processor comprising:

• at least four processor cores, each processor core having a local LEVEL-1 cache including memory for caching data,
• a tree communication structure physically interconnecting the multiple LEVEL-1 caches,
• the tree communication structure having a plurality of nodes, wherein the processor cores with the respective local caches are leaf nodes of the tree communication structure and a LEVEL-2 cache is a root node of the tree communication structure, the LEVEL-2 cache including memory for caching data,
• wherein a plurality of memories for storing TAG information are associated to the memories for caching data of the LEVEL-1 caches, the TAG information referencing the data, wherein each of the memories for storing TAG information is physically located in a respective one of the LEVEL-1 caches, and
• wherein at least some of the nodes are operative to handle multiple accesses or transfers in parallel.

A single package multi-core processor comprising:

• at least two processor cores, each core having a local LEVEL-1 cache including memory for caching data, and
• a tree communication structure physically interconnecting the multiple LEVEL-1 caches, the tree communication structure having at least two levels, wherein
• a first level of the two levels comprises the LEVEL-1 caches, and
• a second level of the two levels comprises at least one higher level cache having a higher level than the LEVEL-1 caches and including memory for caching data,
• wherein the processor cores are operative to access data in each other's LEVEL-1 caches at runtime, and
• wherein a plurality of memories for storing TAG information are associated to the memories for caching data of the LEVEL-1 caches, the TAG information referencing the data, wherein each of the memories for storing TAG information is physically located in a respective one of the LEVEL-1 caches.

A single package processor comprising:

• at least two processor cores, each processor core having a local LEVEL-1 cache including memory for caching data, and
• a tree communication structure physically interconnecting the multiple LEVEL-1 caches, the tree communication structure having a plurality of nodes, wherein the processor cores with the respective local caches are leaf nodes of the tree communication structure and a LEVEL-2 cache is a root node of the tree communication structure, the LEVEL-2 cache including memory for caching data,
• wherein the memory of the LEVEL-1 caches is a local memory;
• wherein physical address space of the local memory in at least one of the local LEVEL-1 caches is defined by a window within a virtual address space;
• and
• wherein a plurality of memories for storing TAG information are associated to the local memories for caching data of the LEVEL-1 caches, the TAG information referencing the data, wherein each of the local memories for storing TAG information is physically located in a respective one of the LEVEL-1 caches.