Multi-petascale highly efficient parallel supercomputer

A scalable, massively parallel computing system comprising:

• a plurality of processing nodes interconnected by independent networks, each processing node including one or more processing elements, said processing elements including one or more processor cores, and a direct memory access (DMA) for performing computation or communication activity as required when performing parallel algorithm operations;
• a first independent network comprising an n-dimensional torus network, where n is an integer greater than 3, including communication links interconnecting said processing nodes in a manner optimized for providing high-speed, low latency point-to-point and multicast packet communications among said processing nodes or sub-sets of processing nodes of said network;
• a plurality of Input/Output (I/O) nodes, a second independent network including an external high-speed network connecting each I/O node to other processing nodes;
• wherein sub-sets of processing nodes are interconnected by divisible portions of said first and second networks for dynamically configuring one or more combinations of independent processing networks according to needs of one or more algorithms,
• wherein each of said configured independent processing networks is utilized to enable simultaneous collaborative processing for optimizing algorithm processing performance, and
• wherein each said processing element is multi-way hardware threaded supporting transactional memory execution and thread level speculation, wherein said one or more processing elements are configured to run speculative threads in parallel,
• wherein each processing element is further configured to:
• communicate with a communications pathway, the pathway comprising a first level cache and a second level cache;
• switch between at least two modes of using the first and second level caches, both modes allowing the first level cache and/or a prefetch unit to be operated in a speculation blind manner, and
• wherein the at least two modes comprise:
• a first mode where, responsive to a write from a speculative thread, at least one line corresponding to results is evicted from the first level cache and/or said prefetch unit and recorded in the second level cache;
• and
• a second mode where, responsive to a write from a speculative thread, the first level cache stores results,
• wherein, in the second mode, upon completion of a speculative thread, the first level cache and/or said prefetch unit is cleared and any data needed by other speculative threads are reloaded from the second level cache;
• and
• in the first mode, the first level cache and/or prefetch unit does not need to be cleared after completion of a speculative thread, and
• wherein responsive to selection of the first mode, said processing element is configured to:
• determine whether a speculative thread seeks to write;
• upon a positive determination, write from the speculative thread through the first level cache to the second level cache;
• evict a line from the first level cache and/or a prefetch unit corresponding to the writing;
• and
• resolve speculation downstream from the first level cache.

A massively parallel computing system comprising:

• a plurality of processing nodes interconnected by multiple independent networks, each processing node comprising:
• a system-on-chip Application Specific Integrated Circuit (ASIC) device comprising two or more processing elements each capable of performing computation or message passing operations, herein said processing elements of a processing node are configured to:
• enable rapid coordination of processing and message passing activity at each said processing element,
• perform, at one or more processing elements, calculations needed by an algorithm, while another of said one or more processing element performs message passing activities for communicating with other processing nodes of an independent network, as required when performing particular classes of algorithms,
• wherein each said processing element is multi-way hardware threaded to support transactional memory execution and thread level speculation execution, wherein said two or more processing elements are configured to run speculative threads in parallel, and
• wherein each processing element is further configured to:
• communicate with a communications pathway, the pathway comprising a first level cache and a second level cache;
• switch between at least two modes of using the first and second level caches, both modes allowing the first level cache and/or a prefetch unit to be operated in a speculation blind manner, and
• wherein the at least two modes comprise:
• a first mode where, responsive to a write from a speculative thread, at least one line corresponding to results is evicted from the first level cache and/or said prefetch unit and recorded in the second level cache;
• and
• a second mode where, responsive to a write from a speculative thread, the first level cache stores results, wherein, in the second mode, upon completion of a speculative thread, the first level cache and/or said prefetch unit is cleared and any data needed by other speculative threads are reloaded from the second level cache;
• and
• in the first mode, the first level cache and/or prefetch unit does not need to be cleared after completion of a speculative thread, and
• wherein responsive to selection of the first mode, said processing element is configured to:
• determine whether a speculative thread seeks to write;
• upon a positive determination, write from the speculative thread through the first level cache to the second level cache;
• evict a line from the first level cache and/or a prefetch unit corresponding to the writing;
• and
• resolve speculation downstream from the first level cache.