# US 9,076,517 B2 · Memory apparatus with gated phase-change memory cells > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,076,517 B2 - Document ID: US9076517B2 - Status: Granted - Kind: B2 - Application number: 13/927,778 - Filed: 2013-06-26 - Published: 2013-12-05 - Granted: 2015-07-07 - Earliest claimed: 2012-05-31 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Gael Close; Daniel Krebs - Web page: https://patentgrep.com/patent/US9076517B2 ## CPC - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 11/5678: {using amorphous/crystalline phase transition storage elements} - G11C 13/0009: {RRAM elements whose operation depends upon chemical change} - G11C 13/003: {Cell access} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 2211/5611: Multilevel memory cell with more than one control gate - G11C 2211/5613: Multilevel memory cell with additional gates, not being floating or control gates - G11C 2213/53: Structure wherein the resistive material being in a transistor, e.g. gate - G11C 2213/75: Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory apparatus includes a plurality of gated phase-change memory cells having s≧2 programmable cell-states, the cells each having a gate and being arranged in series between a source and drain; a bias voltage generator configured to apply a bias voltage to the gate of each cell; and a controller configured to control the bias voltage generator, in a write operation for programming the state of a cell, to apply a first bias voltage to the gate of each cell except an addressed cell for the write operation, wherein application of the first bias voltage to a cell reduces the cell resistance such that application of a programming signal between the source and drain effects programming of the addressed cell only. ## Claims ### Claim 1 A memory apparatus, comprising: a plurality of gated phase-change memory cells having s≧2 programmable cell-states, the cells each having a gate and being arranged in series between a source and drain; a bias voltage generator configured to apply a bias voltage to the gate of each cell; a controller configured to control the bias voltage generator, in a write operation for programming the state of a cell, to apply a first bias voltage to the gate of each cell except a first addressed cell for the write operation, wherein application of the first bias voltage to a cell reduces the cell resistance such that application of a programming signal between the source and drain effects programming only of the addressed cell; wherein the s programmable cell-states include an amorphous RESET state and at least one crystalline state, and further comprising, in the write operation for programming the first addressed cell, reading of the first addressed cell to obtain an indication of cell-state before programming the first addressed cell, and controlling the bias voltage generator by applying a second bias voltage to the gate of the first addressed cell to increase the cell resistance only when programming the first addressed cell from the crystalline state to the RESET state, as determined by indicating the crystalline state from the reading of the first addressed cell, wherein the second bias voltage is not applied when reprogramming the cell from an indicated RESET state to the RESET state. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the controller is configured to control the bias voltage generator, in a read operation for reading the state of a cell, to apply the first bias voltage to the gate of each cell except a second addressed cell for the read operation, wherein application of a read signal between the source and drain permits reading of the second addressed cell by making a read measurement between the source and drain. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein in a read operation, zero bias voltage is applied to the gate of the second addressed cell. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the second bias voltage is set to increase the cell resistance to a value at or near a predetermined maximum value for the crystalline state. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the phase change material is selected such that the Fermi level for the cell in a crystalline state is in or near the conduction band, and wherein the second bias voltage polarity is set at a negative value to move the Fermi level down towards the valence band on applying the second bias voltage. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the phase change material is selected such that the Fermi level for the cell in a crystalline state is in or near the valence band, and wherein the second bias voltage polarity is set at a positive value to move the Fermi level up towards the conduction band on applying the second bias voltage. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the controller is adapted to control the bias voltage generator such that, when programming a cell to a crystalline state, zero bias voltage is applied to the gate of that cell. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the controller is adapted to control the bias voltage generator such that, when programming a cell to the crystalline state, a bias voltage for that state is applied to the gate of the cell to program that state on application of the programming signal. ### Claim 9 (depends on 1) The apparatus of claim 1, further comprising: a signal generator configured to apply a programming signal between the source and drain for programming an addressed cell and for applying a read signal between the source and drain in a read operation for an addressed cell; and a measurement circuit configured to perform a read measurement between the source and drain on application of the read signal to obtain an indication of cell-state for the addressed cell. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein s=2. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein s>2.