Package substrate, method of manufacturing the package substrate and semiconductor package including the package substrate

A method of manufacturing a package substrate, the method comprising:

• forming a first land array on a first surface of an insulating substrate;
• forming a second land array on a second surface of the insulating substrate opposite to the first surface, the second land array including outer lands and inner lands electrically connected to the first land array;
• connecting a first plating line to the outer lands;
• and
• connecting a second plating line between an outer land and an inner land, the second plating line having a width narrower than a width of the first plating line;
• supplying a plating current to the second land array through the first plating line and the second plating line to form a plating layer on the second land array;
• and
• supplying a removing current to the second plating line through the first plating line to remove the second plating line.

A semiconductor package comprising:

• a package substrate including:
• an insulating substrate,
• a first land array arranged on a first surface of the insulating substrate,
• a second land array arranged on a second surface of the insulating substrate opposite to the first surface and electrically connected to the first land array, the second land array including outer lands and inner lands,
• a first plating line connected to the outer lands, and
• a second plating line connected between the outer lands and the inner lands,
• the second plating line having a width narrower than a width of the first plating line, wherein the second plating line is configured to be removed by a removing current, which is supplied through the first plating line;
• a semiconductor chip arranged on the package substrate;
• and
• conductive connecting members electrically connected between the semiconductor chip and the first land array.