Off-plane conductive line interconnects in microelectronic devices
AssigneeIntel Corporation
InventorChuan Hu
Life of this patent
Estimating the term…
Abstract
Off-plane conductive line interconnects may be formed in microelectronic devices. In one example, such as device includes a first set of metal conductive lines in a dielectric substrate at a first horizontal layer of the substrate, a second set of metal conductive lines in the substrate at the first horizontal layer of the substrate and vertically offset from the first set of metal lines, and a dielectric material insulating the metal lines from each other and the first horizontal layer from other horizontal layers. Vias in the dielectric material to connect both the first and second set of metal lines to metal lines at a second horizontal layer of the substrate.
Claims16
An apparatus comprising:
- a dielectric substrate;
- a first set of metal conductive lines in the substrate at a first horizontal layer of the substrate;
- a second set of metal conductive lines in the substrate at the first horizontal layer of the substrate and vertically offset from the first set of metal lines;
- a second horizontal layer of dielectric material over the first horizontal layer and over the first and second sets of metal lines;
- a third set of metal lines directly over the second horizontal layer, wherein the second horizontal dielectric material layer insulates the metal lines from each other and the first horizontal layer from other horizontal layers;
- and
- vias in the second horizontal layer of dielectric material to connect both the first and second set of metal lines to the third set of metal.
A communications device comprising:
- a die having electronic circuitry formed in a dielectric substrate;
- a first set of metal conductive lines in the substrate at a first horizontal layer of the substrate;
- a second set of metal conductive lines in the substrate at the first horizontal layer of the substrate and vertically offset from the first set of metal lines;
- a dielectric material at a second horizontal layer insulating the metal lines from each other and the first horizontal layer from other horizontal layers;
- a third set of metal lines in a third horizontal layer directly over the second horizontal layer;
- and
- vias in the dielectric material to connect both the first and second set of metal lines to the third set of metal lines.
A method comprising:
- patterning a first silicon substrate layer to form a plurality of grooves in the substrate, the grooves being formed below the top of the substrate;
- depositing a conductive material in the grooves of the substrate, the conductive material being formed at different depths of the substrate corresponding to the different depths of the paths to form a first set of metal lines;
- depositing a conductive material over the top of the first substrate layer to form a second set of metal lines
- forming a second silicon layer over the first silicon substrate layer and over the conductive material;
- depositing a third set of metal lines directly over the second silicon layer;
- forming vias through the second silicon layer to connect the first set of metal lines with the third set of meta lines;
- and
- applying additional silcon layers over the vias.
Dependencies are inferred from the claim text.