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US 9,071,554 B2Granted
Timestamp estimation and jitter correction using downstream FIFO occupancy
AssigneeCisco Technology, Inc.
InventorsLuan Bui, Murali Chundi, Subramani Ganesh
Life of this patent
Estimating the term…
Abstract
First, a packet may be received and a timestamp value may be placed on the packet. The timestamp value may comprise a place time value comprising a time when the timestamp was placed on the packet plus a delay time value comprising an estimated time delay between when the timestamp was placed on the packet and when the packet leaves a port exit. Next, the packet may be sent to a first in first out (FIFO) memory. The packet may then be sent from the FIFO memory out the port exit.
Claims22
A method comprising:
- receiving a packet;
- placing a timestamp value on the packet, the timestamp value comprising a place time value comprising a time when the timestamp was placed on the packet plus a delay time value comprising an estimated time delay between when the timestamp was placed on the packet and when the packet leaves a port exit, wherein placing the timestamp value on the packet comprises:
- receiving depth feedback from a first in first out (FIFO) memory indicating the current occupancy of the FIFO memory, and
- calculating the delay time value based upon the received feedback, wherein calculating the delay time value based upon the received feedback comprises multiplying a current FIFO depth as indicated in the received depth feedback by a correction coefficient;
- sending the packet to the FIFO memory;
- and
- sending the packet from the FIFO memory out the port exit.
4 more elements
An apparatus comprising:
- time stamping logic configured to place a timestamp value on a packet, the timestamp value comprising a place time value comprising a time when the timestamp was placed on the packet plus a delay time value comprising an estimated time delay between when the timestamp was placed on the packet and when the packet leaves a port exit, wherein the time stamping logic being configured to place the timestamp value on the packet comprises the time stamping logic being configured to:
- receive depth feedback from a first in first out (FIFO) memory indicating the current occupancy of the FIFO memory;
- and
- calculate the delay time value based upon;
- a first factor derived from multiplying a current FIFO depth as indicated in the received depth feedback by a correction coefficient, and
- a fixed logic delay comprising an estimated time it takes the packet to pass from the time stamping logic to the port exit;
- and
- a port element comprising the FIFO memory and the port exit, the port element configured to;
- receive the timestamped packet,
- place the timestamped packet into the FIFO memory, and
- send the timestamped packet from the FIFO memory out the port exit.
8 more elements
A method comprising:
- placing a timestamp value on a packet, the timestamp value comprising a place time value comprising a time when the timestamp was placed on the packet plus a delay time value comprising an estimated time delay between when the timestamp was placed on the packet and when the packet leaves a port exit, wherein placing the timestamp value on the packet comprises:
- receiving depth feedback from a first in first out (FIFO) memory indicating the current occupancy of the FIFO memory, and
- calculating the delay time value based upon,
- a first factor derived from multiplying a current FIFO depth as indicated in the received depth feedback by a correction coefficient, and
- a fixed logic delay comprising an estimated time it takes the packet to pass from a single, centrally located time stamping logic within an Application Specific Integrated Circuit (ASIC) to the port exit;
- sending the packet to the first in first out (FIFO) memory;
- and
- sending the packet from the first in first out (FIFO) memory out the port exit.
5 more elements
An apparatus comprising:
- time stamping logic configured to place a timestamp value on a packet, the timestamp value comprising a place time value comprising a time when the timestamp was placed on the packet plus a delay time value comprising an estimated time delay between when the timestamp was placed on the packet and when the packet leaves a port exit, wherein the time stamping logic being configured to place the timestamp value on the packet comprises the time stamping logic being configured to calculate the delay time value based upon multiplying a number of outstanding packets by an Inter-Packet Gap (IPG) coefficient;
- and
- a port element comprising a first in first out (FIFO) memory and the port exit, the port element configured to;
- receive the timestamped packet,
- place the timestamped packet into the FIFO memory, and
- send the timestamped packet from the FIFO memory out the port exit.
3 more elements
Dependencies are inferred from the claim text.