High-speed parallel decision feedback equalizer

A high speed equalizer that comprises:

• a front end filter that reduces leading intersymbol interference in a receive signal to provide a filtered signal;
• a serial-to-parallel converter and at least one precompensation unit that together convert the filtered signal into grouped sets of tentative decisions, the sets in each group being made available in parallel;
• a set of pipelined DFE multiplexer units, each multiplexer unit selecting a contingent symbol decision from each set of tentative decisions in each group to form groups of contingent symbol decisions based on a different presumed sequence of preceding symbol decisions;
• and
• an output multiplexer that chooses, based on an actual sequence of preceding symbol decisions, one of said groups of contingent symbol decisions as a group of actual symbol decisions.

A channel interface module that comprises a receiver having:

• a sensor that converts receive channel signals into electrical signals;
• a front end filter that enhances the signal-to-noise ratio of the electrical signals;
• at least one precompensation unit and a serial-to-parallel converter that together produce groups of tentative decision sets, the sets in each group being made available in parallel;
• a set of multiplexer units that each operate on each group to obtain a group of contingent decisions based on a different presumed sequence of preceding symbol decisions;
• an output multiplexer that, based on actual preceding symbol decisions, chooses a group of actual symbol decisions from the groups of contingent decisions;
• and
• a device interface that provides a host node with a received data stream derived from the group of actual symbol decisions.