Method and system for packet synchronization
AssigneeBroadcom Corporation
InventorsBrima Ibrahim, Hea Joung Kim, Henrik Jensen
Life of this patent
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Abstract
A method and system for packet synchronization may comprise receiving a plurality of bits from an incoming sample of data. The received plurality of bits may be sliced at a first sampling rate. A logic level of at least one of the received plurality of bits may be determined based on the slicing of the received plurality of bits. The received plurality of bits may be synchronized with a channel access code based on determining the logic level of at least one of the received plurality of bits. The channel access code may be sampled at a higher frequency, to increase the probability of detecting whether the incoming bit is LOGIC 1 or LOGIC 0.
Claims30
A method for signal processing, the method comprising:
- receiving a plurality of bits for an incoming sample of data;
- slicing said received plurality of bits at a first sampling rate;
- determining a logic level of at least one of said received plurality of bits based on said slicing;
- and
- synchronizing said received plurality of bits with a channel access code based on said determined logic level.
A machine-readable storage having stored thereon, a computer program having at least one code section for signal processing, the at least one code section being executable by a machine for causing the machine to perform steps comprising:
- receiving a plurality of bits for an incoming sample of data;
- slicing said received plurality of bits at a first sampling rate;
- determining a logic level of at least one of said received plurality of bits based on said slicing;
- and
- synchronizing said received plurality of bits with a channel access code based on said determined logic level.
A system for signal processing, the system comprising:
- one or more circuits that are operable to receive a plurality of bits for an incoming sample of data;
- said one or more circuits are operable to slice said received plurality of bits at a first sampling rate;
- said one or more circuits are operable to determine a logic level of at least one of said received plurality of bits based on said slicing;
- and
- said one or more circuits are operable to synchronize said received plurality of bits with a channel access code based on said determined logic level.
Dependencies are inferred from the claim text.