Selective provision of error correction for memory

At least one non-transitory computing device-readable storage medium having executable instructions that, in response to execution by a memory controller, cause the memory controller to:

• recognize an error correction performed to correct one or more errors for one or more storage locations of a non-volatile memory by a first error correction arrangement of the memory, wherein the first error correction arrangement has a first level correction capability;
• determine, in response to the recognition, whether the first level correction capability is sufficient to correct an additional amount of error or errors if subsequently detected for the one or more storage locations;
• based on a result of the determination, selectively employ a second correction arrangement with higher error correction capability than the first correction arrangement to provide additional error correction capability to the one or more storage locations;
• in response to a read request to access a unit of data stored in the non-volatile memory, detect and correct one or more errors, if present, in the group of storage locations using an error correction code provided by the second error correction arrangement;
• and
• in response to detection and correction of a threshold number of errors under the second error correction arrangement, generate an error correction code in accordance with a third error correction arrangement, and replace the error correction code of the second error correction arrangement with the error correction code of the third correction arrangement.

A memory controller-implemented method, comprising:

• recognizing, with a memory controller, an error correction performed to correct one or more errors for one or more storage locations of a non-volatile memory by a first error correction arrangement of the non-volatile memory, wherein the first error correction arrangement has a first level correction capability;
• determining, by the memory controller, in response to the recognition, whether the first level correction capability is sufficient to correct an additional amount of error or errors if subsequently detected for the one or more storage locations;
• based on a result of the determination, selectively employing, by the memory controller, a second correction arrangement with higher error correction capability than the first correction arrangement to provide additional error correction capability to the one or more storage locations;
• detecting and correcting, by the memory controller, one or more errors, if present, in the group of storage locations using an error correction code provided by the second error correction arrangement;
• and
• in response to detecting and correcting a threshold number of errors under the second error correction arrangement, generating, by the memory controller, an error correction code in accordance with a third error correction arrangement, and replacing, by the memory controller, the error correction code of the second error correction arrangement with the error correction code of the third correction arrangement.