US 9,071,276 B2Granted

Data-processing device and data-processing method

AssigneeSony Corporation

InventorsYuji Shinohara, Makiko Yamamoto

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Abstract

The present technology relates to a data-processing device and a data-processing method, which are capable of improving tolerance for an error of data. When an LDPC code having a code length of 16200 bits is mapped to 16 signal points, a demultiplexer performs exchanging such that when a (#i+1)-th bit from a most significant bit of code bits of 4×2 bits and a (#i+1)-th bit from a most significant bit of symbol bits of 4×2 bits of 2 consecutive symbols are represented by a bit b#i and a bit y#i, respectively, for LDPC codes having coding rates of 1/5, 4/15, and 1/3, b0 is allocated to y4, b1 is allocated to y3, b2 is allocated to y2, b3 is allocated to y1, b4 is allocated to y6, b5 is allocated to y5, b6 is allocated to y7, and b7 is allocated to y0. For example, the present invention can be applied to a transmission system that transmits an LDPC code or the like.

Claims13

Dependent claims

A data-processing device, comprising:

an encoding unit that performs LDPC coding in which a code length is 16200 bits and a coding rate is 4/15 based on a parity check matrix of an LDPC code;
and
an exchange unit that exchanges code bits of the encoded LDPC code for symbol bits of a symbol corresponding to one of 16 signal points set in 16QAM,
wherein the encoded LDPC code includes an information bit and a parity bit,
the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit,
the information matrix portion is represented by a parity check matrix initial value table,
the parity check matrix initial value table is a table in which a position of 1 of an element of the information matrix portion is represented for every 360 columns and is formed as follows:
1953 2331 2545 2623 4653 5012 5700 6458 6875 7605 7694 7881 8416 8758 9181 9555 9578 9932 10068 11479 11699
514 784 2059 2129 2386 2454 3396 5184 6624 6825 7533 7861 9116 9473 9601 10432 11011 11159 11378 11528 11598
483 1303 1735 2291 3302 3648 4222 4522 5511 6626 6804 7404 7752 7982 8108 8930 9151 9793 9876 10786 11879
1956 7572 9020 9971
13 1578 7445 8373
6805 6857 8615 11179
7983 8022 10017 11748
4939 8861 10444 11661
2278 3733 6265 10009
4494 7974 10649
8909 11030 11696
3131 9964 10480, and
in an exchange process of exchanging the code bits of 4×2 bits grouped into 3 code bit groups according to an error probability to be allocated to the symbol bits of 4×2 bits grouped into 2 symbol bit groups according to an error probability,
the exchange unit
allocates 1 bit of code bits of a code bit group having the highest error probability to 1 bit of symbol bits of a symbol bit group having the highest error probability,
allocates 1 bit of code bits of a code bit group having the second highest error probability to 1 bit of symbol bits of a symbol bit group having the second highest error probability,
allocates 1 bit of code bits of a code bit group having the third highest error probability to 1 bit of symbol bits of a symbol bit group having the second highest error probability,
allocates 2 bits of code bits of a code bit group having the fourth highest error probability to 2 bits of symbol bits of a symbol bit group having the second highest error probability, and
allocates 3 bits of code bits of a code bit group having the fourth highest error probability to a 3 bits of symbol bits of a symbol bit group having the highest error probability.

23 more elements

A data-processing device, comprising:

an encoding unit that performs LDPC coding in which a code length is 16200 bits and a coding rate is 4/15 based on a parity check matrix of an LDPC code;
and
an exchange unit that exchanges code bits of the encoded LDPC code for symbol bits of a symbol corresponding to one of 16 signal points set in 16QAM,
wherein the encoded LDPC code includes an information bit and a parity bit,
the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit,
the information matrix portion is represented by a parity check matrix initial value table,
the parity check matrix initial value table is a table in which a position of 1 of an element of the information matrix portion is represented for every 360 columns and is formed as follows:
1953 2331 2545 2623 4653 5012 5700 6458 6875 7605 7694 7881 8416 8758 9181 9555 9578 9932 10068 11479 11699
514 784 2059 2129 2386 2454 3396 5184 6624 6825 7533 7861 9116 9473 9601 10432 11011 11159 11378 11528 11598
483 1303 1735 2291 3302 3648 4222 4522 5511 6626 6804 7404 7752 7982 8108 8930 9151 9793 9876 10786 11879
1956 7572 9020 9971
13 1578 7445 8373
6805 6857 8615 11179
7983 8022 10017 11748
4939 8861 10444 11661
2278 3733 6265 10009
4494 7974 10649
8909 11030 11696
3131 9964 10480, and
when code bits of 8 bits that are stored in 8 storing units having a storage capacity of 16200/8 bits and each of which is read from each storing unit are allocated to 2 consecutive symbols, a (#i+1)-th bit from a most significant bit of the code bits of 8 bits is represented by a bit b#i, and a (#i+1)-th bit from a most significant bit of the symbol bits of 8 bits of the 2 symbols is represented by a bit y#i,
the exchange unit exchanges
a bit b0 for a bit y4,
a bit b1 for a bit y3,
a bit b2 for a bit y2,
a bit b3 for a bit y1,
a bit b4 for a bit y6,
a bit b5 for a bit y5,
a bit b6 for a bit y7, and
a bit b7 for a bit y0.

26 more elements

A data-processing method, comprising:

an encoding step of performing LDPC coding in which a code length is 16200 bits and a coding rate is 4/15 based on a parity check matrix of an LDPC code;
and
an exchange step of exchanging code bits of the encoded LDPC code for symbol bits of a symbol corresponding to one of 16 signal points set in 16QAM,
wherein the encoded LDPC code includes an information bit and a parity bit,
the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit,
the information matrix portion is represented by a parity check matrix initial value table,
the parity check matrix initial value table is a table in which a position of 1 of an element of the information matrix portion is represented for every 360 columns and is formed as follows:
1953 2331 2545 2623 4653 5012 5700 6458 6875 7605 7694 7881 8416 8758 9181 9555 9578 9932 10068 11479 11699
514 784 2059 2129 2386 2454 3396 5184 6624 6825 7533 7861 9116 9473 9601 10432 11011 11159 11378 11528 11598
483 1303 1735 2291 3302 3648 4222 4522 5511 6626 6804 7404 7752 7982 8108 8930 9151 9793 9876 10786 11879
1956 7572 9020 9971
13 1578 7445 8373
6805 6857 8615 11179
7983 8022 10017 11748
4939 8861 10444 11661
2278 3733 6265 10009
4494 7974 10649
8909 11030 11696
3131 9964 10480, and
in an exchange process of exchanging code bits of 4×2 bits grouped into 3 code bit groups according to an error probability to be allocated to symbol bits of 4×2 bits grouped into 2 symbol bit groups according to an error probability,
the exchange step includes
allocating 1 bit of code bits of a code bit group having the highest error probability to 1 bit of symbol bits of a symbol bit group having the highest error probability,
allocating 1 bit of code bits of a code bit group having the second highest error probability to 1 bit of symbol bits of a symbol bit group having the second highest error probability,
allocating 1 bit of code bits of a code bit group having the third highest error probability to 1 bit of symbol bits of a symbol bit group having the second highest error probability,
allocating 2 bits of code bits of a code bit group having the fourth highest error probability to 2 bits of symbol bits of a symbol bit group having the second highest error probability, and
allocating 3 bits of code bits of a code bit group having the fourth highest error probability to 3 bits of symbol bits of a symbol bit group having the highest error probability.

23 more elements

A data-processing method, comprising:

an encoding step of performing LDPC coding in which a code length is 16200 bits and a coding rate is 4/15 based on a parity check matrix of an LDPC code;
and
an exchange step of exchanging code bits of the encoded LDPC code for symbol bits of a symbol corresponding to one of 16 signal points set in 16QAM,
wherein the encoded LDPC code includes an information bit and a parity bit,
the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit,
the information matrix portion is represented by a parity check matrix initial value table,
the parity check matrix initial value table is a table in which a position of 1 of an element of the information matrix portion is represented for every 360 columns and is formed as follows:
1953 2331 2545 2623 4653 5012 5700 6458 6875 7605 7694 7881 8416 8758 9181 9555 9578 9932 10068 11479 11699
514 784 2059 2129 2386 2454 3396 5184 6624 6825 7533 7861 9116 9473 9601 10432 11011 11159 11378 11528 11598
483 1303 1735 2291 3302 3648 4222 4522 5511 6626 6804 7404 7752 7982 8108 8930 9151 9793 9876 10786 11879
1956 7572 9020 9971
13 1578 7445 8373
6805 6857 8615 11179
7983 8022 10017 11748
4939 8861 10444 11661
2278 3733 6265 10009
4494 7974 10649
8909 11030 11696
3131 9964 10480, and
when code bits of 8 bits that are stored in 8 storing units having a storage capacity of 16200/8 bits and each of which is read from each storing unit are allocated to 2 consecutive symbols, a (#i+1)-th bit from a most significant bit of the code bits of 8 bits is represented by a bit b#i, and a (#i+1)-th bit from a most significant bit of the symbol bits of 8 bits of the 2 symbols is represented by a bit y#i, the exchange step includes exchanging
a bit b0 for a bit y4,
a bit b1 for a bit y3,
a bit b2 for a bit y2,
a bit b3 for a bit y1,
a bit b4 for a bit y6,
a bit b5 for a bit y5,
a bit b6 for a bit y7, and
a bit b7 for a bit y0.

25 more elements

A data-processing device, comprising:

a reverse exchange unit that exchanges symbol bits of a symbol corresponding to one of 16 signal points set in 16QAM for code bits of an LDPC code in which a code length is 16200 bits and a coding rate is 4/15;
and
a decoding unit that decodes the LDPC code exchanged by the reverse exchange unit based on a parity check matrix of the LDPC code,
wherein when code bits of 8 bits that are stored in 8 storing units having a storage capacity of 16200/8 bits and each of which is read from each storing unit are allocated to 2 consecutive symbols, a (#i+1)-th bit from a most significant bit of the code bits of 8 bits is represented by a bit b#i, and a (#i+1)-th bit from a most significant bit of the symbol bits of 8 bits of the 2 symbols is represented by a bit y#i, the reverse exchange unit exchanges
a bit y4 for a bit b0,
a bit y3 for a bit b1,
a bit y2 for a bit b2,
a bit y1 for a bit b3,
a bit y6 for a bit b4,
a bit y5 for a bit b5,
a bit y7 for a bit b6, and
a bit y0 for a bit b7,
the LDPC code includes an information bit and a parity bit,
the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit,
the information matrix portion is represented by a parity check matrix initial value table, and
the parity check matrix initial value table is a table in which a position of 1 of an element of the information matrix portion is represented for every 360 columns and is formed as follows:
1953 2331 2545 2623 4653 5012 5700 6458 6875 7605 7694 7881 8416 8758 9181 9555 9578 9932 10068 11479 11699
514 784 2059 2129 2386 2454 3396 5184 6624 6825 7533 7861 9116 9473 9601 10432 11011 11159 11378 11528 11598
483 1303 1735 2291 3302 3648 4222 4522 5511 6626 6804 7404 7752 7982 8108 8930 9151 9793 9876 10786 11879
1956 7572 9020 9971
13 1578 7445 8373
6805 6857 8615 11179
7983 8022 10017 11748
4939 8861 10444 11661
2278 3733 6265 10009
4494 7974 10649
8909 11030 11696
3131 9964 10480.

25 more elements

A data-processing method, comprising:

a reverse exchange step of exchanging symbol bits of a symbol corresponding to one of 16 signal points set in 16QAM for code bits of an LDPC code in which a code length is 16200 bits and a coding rate is 4/15;
and
a decoding step of decoding the LDPC code exchanged in the reverse exchange step based on a parity check matrix of the LDPC code,
wherein
when code bits of 8 bits that are stored in 8 storing units having a storage capacity of 16200/8 bits and each of which is read from each storing unit are allocated to 2 consecutive symbols, a (#i+1)-th bit from a most significant bit of the code bits of 8 bits is represented by a bit b#i, and a (#i+1)-th bit from a most significant bit of the symbol bits of 8 bits of the 2 symbols is represented by a bit y#i, the reverse exchange step includes exchanging
a bit y4 for a bit b0,
a bit y3 for a bit b1,
a bit y2 for a bit b2,
a bit y1 for a bit b3,
a bit y6 for a bit b4,
a bit y5 for a bit b5,
a bit y7 for a bit b6, and
a bit y0 for a bit b7,
the LDPC code includes an information bit and a parity bit,
the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit,
the information matrix portion is represented by a parity check matrix initial value table, and
the parity check matrix initial value table is a table in which a position of 1 of an element of the information matrix portion is represented for every 360 columns and is formed as follows:
1953 2331 2545 2623 4653 5012 5700 6458 6875 7605 7694 7881 8416 8758 9181 9555 9578 9932 10068 11479 11699
514 784 2059 2129 2386 2454 3396 5184 6624 6825 7533 7861 9116 9473 9601 10432 11011 11159 11378 11528 11598
483 1303 1735 2291 3302 3648 4222 4522 5511 6626 6804 7404 7752 7982 8108 8930 9151 9793 9876 10786 11879
1956 7572 9020 9971
13 1578 7445 8373
6805 6857 8615 11179
7983 8022 10017 11748
4939 8861 10444 11661
2278 3733 6265 10009
4494 7974 10649
8909 11030 11696
3131 9964 10480.

26 more elements

A data-processing device, comprising:

a reverse exchange unit that exchanges symbol bits of a symbol corresponding to one of 16 signal points set in 16QAM for code bits of an LDPC code in which a code length is 16200 bits and a coding rate is 1/5;
and
a decoding unit that decodes the LDPC code exchanged by the reverse exchange unit based on a parity check matrix of the LDPC code,
wherein when code bits of 8 bits that are stored in 8 storing units having a storage capacity of 16200/8 bits and each of which is read from each storing unit are allocated to 2 consecutive symbols, a (#i+1)-th bit from a most significant bit of the code bits of 8 bits is represented by a bit b#i, and a (#i+1)-th bit from a most significant bit of the symbol bits of 8 bits of the 2 symbols is represented by a bit y#i, the reverse exchange unit exchanges
a bit y4 for a bit b0,
a bit y3 for a bit b1,
a bit y2 for a bit b2,
a bit y1 for a bit b3,
a bit y6 for a bit b4,
a bit y5 for a bit b5,
a bit y7 for a bit b6, and
a bit y0 for a bit b7,
the LDPC code includes an information bit and a parity bit,
the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit,
the information matrix portion is represented by a parity check matrix initial value table, and
the parity check matrix initial value table is a table in which a position of 1 of an element of the information matrix portion is represented for every 360 columns and is formed as follows:
188 518 775 1694 1820 3394 3986 4140 4224 5236 5783 6313 6371 6792 7067 7084 7173 7445 7549 7973 9043 9219 9942 10111 10258 10300 10353 10707 10769 10796 11079 11661 12025 12042 12702 12838
7 25 392 557 625 838 1377 2223 2396 3058 3335 3348 3363 3918 4040 4128 4899 5189 5474 5838 6040 6124 7777 8220 8783 9299 9785 10924 11083 11902 12381 12513 12758 12834 12871 12950
76 4691 7180 7325 11292
6454 8048 12058 12946
3953 4932 10808 12700
4605 9117 9921 10662
2984 8202 10670 12877
4357 6205 7370 10403
5559 9847 10911 11147.

22 more elements

A data-processing device, comprising:

a reverse exchange unit that exchanges symbol bits of a symbol corresponding to one of 16 signal points set in 16QAM for code bits of an LDPC code in which a code length is 16200 bits and a coding rate is 1/3;
and
a decoding unit that decodes the LDPC code exchanged by the reverse exchange unit based on a parity check matrix of the LDPC code,
wherein when code bits of 8 bits that are stored in 8 storing units having a storage capacity of 16200/8 bits and each of which is read from each storing unit are allocated to 2 consecutive symbols, a (#i+1)-th bit from a most significant bit of the code bits of 8 bits is represented by a bit b#i, and a (#i+1)-th bit from a most significant bit of the symbol bits of 8 bits of the 2 symbols is represented by a bit y#i, the reverse exchange unit exchanges
a bit y4 for a bit b0,
a bit y3 for a bit b1,
a bit y2 for a bit b2,
a bit y1 for a bit b3,
a bit y6 for a bit b4,
a bit y5 for a bit b5,
a bit y7 for a bit b6, and
a bit y0 for a bit b7,
the LDPC code includes an information bit and a parity bit,
the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit,
the information matrix portion is represented by a parity check matrix initial value table, and
the parity check matrix initial value table is a table in which a position of 1 of an element of the information matrix portion is represented for every 360 columns and is formed as follows:
77 182 354 816 916 958 1055 1261 1553 1874 2211 2490 2999 3267 3975 5018 5952 6198 6343 7027 7045 7751 7923 8649 9010 9022 9380 9956 10204 10339
5 612 1724 1737 1911 1914 2108 2496 2809 4037 5838 6950 8049 8081 9480 9512 9724 9745 9952 10203 10207 10270 10463 10486 10499 10515 10663 10678 10706 10741
22 345 1938 3636 4016 5293 6424 6589 7426 7547 8102 9038 9095 9127 9174 9239 9279 9810 10347 10403 10408 10591 10610 10632 10660 10721 10754 10765 10773 10791 17 3435 7278 9952
1442 2518 3132 7541
5464 9226 10615 10658
426 2473 8459 10750
1862 2111 6236 10546
1010 9922 10591 10735
29 2663 6553 10749
5652 7265 7789 10708
4534 5497 10784
345 3027 10761
2823 4127 10668
84 4800 9068.

27 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/997,695Filed 12 Jan 2012
Priority: JP 2011-00875219 Jan 2011
Published: US 2013/0290816 A131 Oct 2013
Granted: 30 Jun 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H03M 13/13
Using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits: linear codes
H03M 13/036
Theoretical methods to calculate these checking codes: heuristic code construction methods, i.e. code construction or code search based on using…
H03M 13/1165
Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices: qC-LDPC codes as defined…
H03M 13/255
Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded…: with…