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US 9,071,273 B2Granted
Extended single-bit error correction and multiple-bit error detection
AssigneeMicron Technology, Inc.
InventorDavid R. Resnick
Life of this patent
Estimating the term…
Abstract
Some embodiments include apparatus and methods to prevent at least one of misidentifying and ignoring multiple-bit errors if the multiple-bit errors include a plurality of erroneous data bits that belong to only one specific group of a plurality of groups of data bits and if none of the other groups of the plurality of groups have errors.
Claims20
An apparatus comprising:
- lines configured to transfer information that includes groups, each of the groups including bits, each of the lines configured to serially transfer the bits of one of the groups in a plurality of transfers;
- and
- a module configured to implement a matrix that includes a first portion to enable detection of errors in a number of transfers among the plurality of transfers and a second portion to enable identifying whether the detected errors have occurred to bits of one of the groups.
An apparatus comprising:
- lines configured to transfer information that includes groups;
- and
- a module configured to:
- assign an identification to each of the groups in information;
- identify the identification of a specific group among groups if a single erroneous bit has occurred in the information and if the single erroneous bit belongs to the specific group;
- and
- prevent at least one of misidentifying and ignoring multiple-bit errors if the multiple-bit errors include a plurality of erroneous data bits that belong to the specific group and if none of the other groups of the plurality of groups have errors.
4 more elements
A system comprising:
- a controller;
- a memory device;
- and
- a module configured to transfer information between the memory device and the controller in plurality of transfers, the information including groups, each of the groups including bits and to implement a matrix that includes a first portion to enable detection of errors in a number of transfers among the plurality of transfers and a second portion to enable identifying whether the detected errors have occurred to bits of one of the groups.
1 more element
Dependencies are inferred from the claim text.