Time-interleaved analog-to-digital converter bandwidth matching
AssigneeCrest Semiconductors, Inc.
InventorsTracy Johancsik, Ryan James Kier, Yusuf Haque
Life of this patent
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Abstract
A time-interleaved Analog-to-Digital Converter (ADC) includes a set of time multiplexed sub-ADC circuits, each sub-ADC circuit comprising a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a track mode and a hold mode, and a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects the voltage level.
Claims16
A time-interleaved Analog-to-Digital Converter (ADC) comprising:
- a number of sub-ADC circuits;
- wherein each said sub-ADC comprises a sample-and-hold circuit;
- wherein each said sample-and-hold circuit comprises:
- a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of said switch, said switch for switching between a sample mode and a hold mode;
- and
- wherein said bootstrap circuit is used to further adjust said constant voltage level between said input terminal and said gate terminal of said switch to adjust an ON state of an intrinsic resistance of said switch.
A method for matching bandwidths within a time-interleaved Analog-to-Digital Converter (ADC), the method comprising:
- determining a frequency response of a sample-and-hold circuit for each of a set of sub-ADC circuits within a time-interleaved ADC;
- and
- adjusting a bandwidth of at least one of said sub-ADC circuits by adjusting an intrinsic resistance of an ON state of a switch associated with a sample-and-hold circuit of said at least one of said sub-ADC circuits, said adjusting causing bandwidths among said sub-ADC circuits to be more closely matched.
Dependencies are inferred from the claim text.