Successive approximation analog-to-digital converter with linearity error correction

A method for compensating for an error during an analog-to-digital conversion cycle of an analog-to-digital converter (ADC) that receives an analog input signal and generates a corresponding digital output value, wherein the ADC includes a plurality of capacitors that include first and second sets of capacitors and an error-detection capacitor, the method comprising:

• sampling the analog input signal across the plurality of capacitors during a sampling cycle of the analog-to-digital conversion cycle;
• generating a first set of voltage signals with the first set of capacitors during a first set of comparison cycles of a plurality of comparison cycles of the analog-to-digital conversion cycle;
• generating a first set of control signals based on a comparison of the first set of voltage signals and a common-mode voltage signal;
• generating a first set of bits corresponding to the first set of voltage signals by performing a first successive approximation using the first set of control signals;
• generating an error-detection voltage signal by the error-detection capacitor during an error-detection comparison cycle of the plurality of comparison cycles;
• generating an error-detection control signal based on a comparison of the error-detection voltage signal and the common-mode voltage signal;
• compensating for an error in the first set of bits based on the error-detection control signal;
• generating a second set of voltage signals with the second set of capacitors during a second set of comparison cycles of the plurality of comparison cycles;
• generating a second set of control signals based on a comparison of the second set of voltage signals and the common-mode voltage signal;
• and
• generating a second set of bits corresponding to the second set of voltage signals by performing a second successive approximation using the second set of control signals, wherein the first and second sets of bits correspond to the digital output value.

An analog-to-digital converter (ADC), comprising:

• a plurality of capacitors having respective first terminals for receiving an analog input signal during a sampling cycle of an analog-to-digital conversion cycle, and respective second terminals connected together at a first node, wherein the plurality of capacitors comprise a first set of capacitors that generate a first set of voltage signals at the first node during a first set of comparison cycles of a plurality of comparison cycles of the analog-to-digital conversion cycle, an error-detection capacitor that generates an error-detection voltage signal at the first node during an error-detection comparison cycle of the plurality of comparison cycles, and a second set of capacitors that generate a second set of voltage signals at the first node during a second set of comparison cycles of the plurality of comparison cycles;
• a comparator having a first input terminal connected to the first node for receiving the first set of voltage signals at the end of corresponding first set of comparison cycles, the second set of voltage signals at the end of corresponding second set of comparison cycles, and the error-detection voltage signal at the end of the error-detection comparison cycle, a second input terminal for receiving a common-mode voltage signal, and an output terminal for outputting a first set of control signals at the end of corresponding first set of comparison cycles, an error-detection control signal at the end of the error-detection comparison cycle, and a second set of control signals at the end of corresponding second set of comparison cycles;
• a successive-approximation register (SAR) logic circuit, connected to the output terminal of the comparator, that generates a first set of bits corresponding to the first set of voltage signals by running a first successive approximation using the first set of control signals, compensates an error in the first set of bits based on the error-detection control signal, and generates a second set of bits corresponding to the second set of voltage signals by running a second successive approximation using the second set of control signals, wherein the first and second sets of bits correspond to a binary representation of the analog input signal;
• and
• an AND gate, connected to the SAR logic circuit, for receiving the first set of bits and generating a first logic signal, wherein the SAR logic circuit compensates the error in the first set of bits based on the first logic signal.