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US 9,071,261 B2Granted
Accuracy enhancement techniques for ADCs
AssigneeAnalog Devices, Inc.
InventorsJunhua Shen, Ronald A. Kapusta
Life of this patent
Estimating the term…
Abstract
Embodiments of the present invention may provide accuracy enhancement techniques to improve ADC SNRs. For example, regular bit trials from a most significant bit (MSB) to predetermined less significant bit of a digital word and extra bit trials may be performed. The results of the regular and extra bit trials may be combined to generate a digital output signal. A residue error may be measured, and the digital output signal may be adjusted based on the measured residue error.
Claims24
A method, comprising:
- performing bit trials, using a SAR ADC including a comparator, to convert an analog input signal into a digital output signal;
- after completing the bit trials, performing a plurality of comparator decisions by the comparator with a residue error as an input to the comparator;
- based on the comparator decisions, measuring a residue voltage at the input of the comparator;
- and
- adjusting the digital output signal based on the measured residue error value.
2 more elements
A method, comprising:
- performing regular bit trials using a SAR ADC to convert an analog input signal into a digital output signal for each bit position from a most significant bit (MSB) to a least significant bit (LSB) of the ADC;
- in addition to the regular bit trials, performing repeat bit trials of select regular bit trial(s) at an equal and/or lower magnitude than a predetermined less significant bit trial, wherein each repeat bit trial is weighted the same as its corresponding regular bit trial;
- and
- summing the results of the regular bit trials and the repeat bit trials based on their corresponding bit weights to generate the digital output signal.
1 more element
A method, comprising:
- performing regular bit trials using a comparator from a most significant bit (MSB) to a least significant bit (LSB) of a digital word;
- performing repeat bit trials of select regular bit trials at an equal and/or lower magnitude than a predetermined less significant bit trial, wherein each repeat bit trial is weighted the same as its corresponding regular bit trial;
- summing results of the regular and repeat bit trials based on their corresponding bit weights to generate a digital output signal;
- measuring a residue error by performing a plurality of comparator decisions by the comparator used to perform the regular bit trials with the residue error as an input;
- and
- adjusting the digital output signal based on the measured residue error.
3 more elements
A circuit, comprising:
- a digital-to-analog (DAC) including a plurality of weighted components for performing bit trials;
- a comparator coupled to the DAC for performing the bit trials;
- and a
- successive approximation register (SAR) logic to control the bit trials,
- wherein the comparator is configured to perform a number of comparisons with residue error inputs after completion of the bit trials and wherein the circuit is configured to measure residue error based on the comparisons.
2 more elements
Dependencies are inferred from the claim text.