Parallel-serial converter circuit
AssigneeKabushiki Kaisha Toshiba
InventorMikio Shiraishi
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Abstract
A parallel-serial converter circuit has a frequency divider configured to generate a frequency-divided signal by dividing a frequency of a reference clock signal by a dividing ratio depending on a logic of a speed control signal, a timing pulse generator configured to generate a timing pulse signal based on the frequency-divided signal, a load signal generator configured to generate a load signal based on the speed control signal and the timing pulse signal, a bit clock generator configured to generate a bit clock signal based on the speed control signal and the timing pulse signal, and a parallel-serial converter configured to newly load the parallel data in synchronization with the load signal and convert the loaded parallel data into serial data in synchronization with the bit clock signal.
Claims20
A parallel-serial converter circuit comprising:
- a frequency divider configured to generate a frequency-divided signal by dividing a frequency of a reference clock signal by a dividing ratio depending on a logic of a speed control signal;
- a timing pulse generator configured to generate a timing pulse signal based on the frequency-divided signal;
- a load signal generator configured to generate a load signal based on the speed control signal and the timing pulse signal;
- a bit clock generator configured to generate a bit clock signal based on the speed control signal and the timing pulse signal;
- and
- a parallel-serial converter configured to newly load the parallel data in synchronization with the load signal and convert the loaded parallel data into serial data in synchronization with the bit clock signal.
A parallel-serial converter circuit comprising:
- a master signal transmitter;
- and
- n slave signal transmitters, where n is an integer of 1 or greater,
- wherein the master signal transmitter comprises:
- a first frequency divider configured to generate a first frequency-divided signal by dividing a frequency of a reference clock signal by a dividing ratio depending on a logic of a first speed control signal;
- a first timing pulse generator configured to generate a first timing pulse signal based on the first frequency-divided signal;
- a first load signal generator configured to generate a first load signal based on the first speed control signal and the first timing pulse signal;
- a first bit clock generator configured to generate a first bit clock signal based on the first speed control signal and the first timing pulse signal;
- and
- a first parallel-serial converter configured to newly load the parallel data in synchronization with the first load signal and convert the loaded parallel data into serial data in synchronization with the first bit clock signal,
- each of the n slave signal transmitters comprises:
- a second frequency divider configured to generate a second frequency-divided signal by dividing a frequency of a reference clock signal by a dividing ratio depending on a logic of a second speed control signal;
- a second timing pulse generator configured to generate a second timing pulse signal based on the second frequency-divided signal;
- a second load signal generator configured to generate a second load signal based on the second speed control signal and the second timing pulse signal;
- a second bit clock generator configured to generate a second bit clock signal based on the second speed control signal and the second timing pulse signal;
- and
- a second parallel-serial converter configured to newly load the parallel data in synchronization with the second load signal and convert the loaded parallel data into serial data in synchronization with the second bit clock signal, and
- when the first speed control signal and the second speed control signal have an identical signal logic, the second timing pulse generator generates the timing pulse signal based on the first frequency-divided signal.
Dependencies are inferred from the claim text.