Method for link resets in a SerDes system
AssigneeCadence Design Systems, Inc.
InventorsLoren Blair Reiss, Chris Moscone, Benjamin Louis Heilmann, Randall Smith
Life of this patent
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Abstract
The present disclosure relates to a method for use with a serializer/deserializer comprising. The method may include grouping one or more lane modules associated with an integrated circuit (IC) together to form a link, wherein each of the one or more lane modules includes a reset state machine and a high speed reset generator. The method may also include providing a common module having a common reset release state machine and a reset release synchronizer and pulse generator, the common module and one or more lane modules being configured to communicate therebetween. The method may further include resetting each link independently using the one or more lane modules.
Claims20
A method for use with a serializer/deserializer comprising:
- grouping one or more lane modules associated with an integrated circuit (IC) together to form one or more links, wherein each of the one or more lane modules includes a reset state machine and a high speed reset generator;
- providing a common module having a common reset release state machine and a reset release synchronizer and pulse generator, the common module and one or more lane modules being configured to communicate therebetween;
- and
- resetting each link independently using the one or more lane modules.
An apparatus, comprising:
- an integrated circuit (IC) including one or more lane modules grouped together to form one or more links and a common module having a common reset release state machine and a reset release synchronizer and pulse generator, wherein each of the one or more lane modules includes a reset state machine and a high speed reset generator, and wherein each link is capable of being reset independently of another link.
A method for use with a serializer/deserializer comprising:
- grouping one or more lane modules associated with an integrated circuit (IC) together to form one or more links, wherein each of the one or more lane modules includes a reset state machine and a high speed reset generator;
- providing a common module having a common reset release state machine, the common module and one or more lane modules being configured to communicate therebetween;
- and
- resetting each link independently using the one or more lane modules.
Dependencies are inferred from the claim text.