MOS transistor drain-to-gate leakage protection circuit and method therefor

A first circuit having an active mode and a sleep mode, comprising:

• a power transistor having a first current electrode coupled to a first power supply terminal, a second current electrode as an output of the first circuit for coupling to a load, and a first control electrode, wherein the power transistor is characterized by having a threshold voltage and a leakage current, wherein the leakage current occurs between the first control electrode and the first current electrode during the sleep mode;
• an amplifier having an output coupled to the first control electrode of the power transistor that provides an active output during the active mode;
• and
• a protection circuit that detects the leakage current and prevents the leakage current from developing a voltage on the first control electrode of the power transistor that exceeds the threshold voltage of the power transistor, wherein the protection circuit includes:
• a first transistor having a third current electrode coupled to the first control electrode of the power transistor, a second control electrode, and a fourth current electrode coupled to the output of the first circuit, and
• a current mirror circuit coupled to the first power supply terminal and having a first current mirror input coupled to the first control electrode of the power transistor, a second current mirror input coupled to receive a sleep signal, a first current mirror output coupled to the second control electrode of the first transistor, and a second current mirror output coupled to the output of the first circuit, wherein the current minor circuit comprises:
• a current mirror coupled to the first power supply terminal having a first leg and a second leg;
• a second transistor having a third control electrode as the first current mirror input, a fifth current electrode coupled to the first leg, and a sixth current electrode coupled to the second current minor output;
• a load circuit having a first terminal coupled to the second control electrode of the first transistor and a second terminal coupled to the second current mirror output;
• and
• an input transistor having a fourth control electrode as the second current mirror input, a seventh current electrode coupled to the second leg, and an eighth current electrode coupled to the first power supply terminal.

A method that is for operating a power transistor using a sleep mode and an active mode, wherein during the sleep mode the power transistor has a leakage current between a control electrode and a current electrode, wherein the power transistor has a threshold voltage, comprising:

• applying an input signal to the control electrode of the power transistor during the active mode;
• detecting the leakage current during the sleep mode;
• and
• responsive to detecting the leakage current, providing a current drain on the control electrode of the power transistor during the sleep mode of sufficient magnitude to pull down a voltage on the control electrode of the power transistor to ensure that the threshold voltage of the power transistor is not exceeded during the sleep mode.