US 9,071,246 B2Granted

Memory controller for heterogeneous configurable integrated circuits

AssigneeAgate Logic, Inc.

InventorsSuresh Subramaniam, Mukunda Krishnappa, Pohrong R. Chu, Jason Golbus, Dana L. How

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Abstract

A system including a configurable memory controller, a memory interface, and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array and operable to implement a plurality of pipelined buses, where the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, where the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, where the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface, and where the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit.

Claims19

Dependent claims

A system comprising:

a configurable memory controller including a plurality of configuration bits configured to indicate at least one of memory type, address, data width, and operating frequency;
wherein the configurable memory controller comprise a configuration registers to store the plurality of the configuration bits and a mode register bits;
a dedicated interface coupled to the configuration registers by a mode register data bus, wherein the dedicated interface is used by the user for setting the values in the configuration registers;
a memory interface;
and
a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array wherein each of the plurality of interconnect stations includes a first set of connectors and a second set of connectors wherein the first set of connectors is configured to couple to an adjacent interconnect station via a plurality of pipelined buses,
wherein the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations,
wherein the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations,
wherein the second set of connectors is configured to connect to a programmable logic block (“PLB”).

6 more elements

A programmable logic system comprising:

a configurable memory controller having a configuration register capable of providing memory configuration;
wherein the configuration register includes a plurality of mode register bits, and a plurality of configuration bits, wherein the plurality of configuration bits are programmable to indicate memory type, memory address, data width, and operating frequency;
a dedicated interface coupled to the configuration registers by a mode register data bus, wherein the dedicated interface is used by the user for setting the values in the configuration registers;
a memory interface coupled to the configurable memory controller and configured to include a configurable general purpose input/output (GPIO) block coupled to the configurable memory controller using the first and the second interconnect stations of the plurality of interconnect stations;
and
a configurable high speed communications fabric coupled to the configurable memory controller and including a plurality of interconnect stations arranged in an array wherein each of the plurality of interconnect stations includes a set of ports and a set of ramps wherein the set of ramps is configured to couple to an adjacent interconnect station via a plurality of pipelined buses, wherein the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/855,740Filed 14 Sep 2007
Published: US 2009/0072856 A119 Mar 2009
Granted: 30 Jun 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

G06F 30/343
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: logical level
G06F 13/1668
For access to memory bus: details of memory controller
G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]