Contention-free level converting flip-flops for low-swing clocking
AssigneeCadence Design Systems, Inc.
InventorRadu Zlatanovici
Life of this patent
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Abstract
The present invention includes a family of level converting flip-flops that accepts data and clock inputs at a lower voltage level while producing data outputs at a higher voltage level. These flip-flops enable fine-grained dual supply voltage techniques such as low-swing clocking (distributing the clock signal at a lower voltage level) and clustered voltage scaling (CVS). The level conversion is accomplished in a very efficient manner by sharing the positive feedbacks inside a flip-flop for both storage and level conversion. Additionally, the presented flip-flops are contention-free and non-ratioed, thus having reduced timing and power overheads due to the level conversion function.
Claims23
A level converting flip-flop for low swing-clocking comprising:
- a slave latch comprising a first device and a second device, wherein
- the first device coupled to the second device and the second device are contention-free when the second device is in an on state and the first device is in a leaky off state;
- a level conversion circuitry, including a feedback loop that is shared between storage function and level-conversion function of the level converting flip-flop, to convert an output prior to transmission to the slave latch;
- and
- a master latch to generate the output and communicate with the slave latch, wherein the level converting flip-flop is non-ratioed.
A computer program product embodied on a non-transitory, tangible computer usable medium, the computer usable medium having stored thereon a sequence of instructions which, when executed by a processor, causes the processor to execute a process for designing a circuit that contains at least one level-converting flip-flop, the process comprising:
- providing, to a level converting flip-flop, at least a data signal and a clock signal at a first swing voltage, wherein the the level converting flip-flow includes a first device and a second device coupled to the first device;
- performing, by using a processor, level conversion for an output signal of a master latch prior to transmitting a converted output signal to a slave latch and storage of the converted output signal by using at least a level conversion circuitry of the level converting flip-flop, wherein
- the first device and the second device are contention-free when the second device is in an on state and the first device is in a leaky off state;
- sharing a feedback loop of the level conversion circuitry between storage function and level-conversion function of the level converting flip-flop;
- and
- outputting from the level converting flip-flop at least one output signal, wherein the output signal is at a second swing voltage.
A method for synthesizing a circuit design that includes at least one level-converting flip-flop, comprising:
- providing to a level converting flip-flop at least a data signal and a clock signal at a first swing voltage, wherein the level converting flip-flop comprises a first device and a second device coupled to the first device;
- performing, by using a processor, level conversion for an output signal of a master latch prior to transmitting a converted output signal to a slave latch and storage of the converted output signal by using at least a level conversion circuitry of the level converting flip-flop, wherein
- the level-converting flip-flop is non-ratioed, and
- the first device and the second device are contention-free when the second device is in an on state and the first device is in a leaky off state;
- sharing a feedback loop of the level conversion circuitry between storage function and level-conversion function of the level converting flip-flop;
- and
- outputting from the level converting flip-flop at least one output signal, wherein the output signal is at a second swing voltage.
Dependencies are inferred from the claim text.