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US 9,071,230 B2Granted
Gate driving circuit and display apparatus having the same
AssigneeSamsung Display Co., Ltd.
InventorsJong-Hee Kim, Yeong-Keun Kwon, Ji-Sun Kim, Jae-Keun Lim, ChongChel Chai
Life of this patent
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Abstract
A gate driving circuit and a display apparatus having the gate driving circuit, in which the gate driving circuit includes a voltage adjusting part using a low clock signal to increase the reliability of the gate driving circuit, thereby extending the lifetime of the gate driving circuit.
Claims20
A gate driving circuit comprising:
- a pull-up control part configured to apply a carry signal of a previous stage to a first node in response to the carry signal of the previous stage;
- a pull-up part configured to output a clock signal as an N-th gate output signal in response to a signal applied to the first node;
- a carry part configured to output the clock signal as an N-th carry signal in response to the signal applied to the first node;
- a first voltage adjusting part configured to output a low clock signal to a second node in response to the signal applied to the first node;
- a first pull-down part configured to pull down the signal at the first node to a second “off” voltage in response to a carry signal of a subsequent stage;
- and
- a second pull-down part configured to pull down the N-th gate output signal to a first “off” voltage in response to the carry signal of the subsequent stage,
- wherein N is a positive integer.
5 more elements
A display apparatus comprising:
- a display panel comprising a display region on which an image is displayed, and a peripheral region adjacent to the display region;
- a data driving circuit configured to apply a data voltage to the display panel;
- and
- a gate driving circuit configured to apply a gate output signal to the display panel,
- wherein the gate driving circuit comprises:
- a pull-up control part configured to apply a carry signal of a previous stage to a first node in response to the carry signal of one of the previous stages;
- a pull-up part configured to output a clock signal as an N-th gate output signal in response to a signal applied to the first node;
- a carry part configured to output the clock signal as an N-th carry signal in response to the signal applied to the first node;
- a first voltage adjusting part configured to output a low clock signal to a second node in response to the signal applied to the first node;
- a first pull-down part configured to pull down the signal at the first node to a second “off” voltage in response to a carry signal of one of next stages;
- and
- a second pull-down part configured to pull down the N-th gate output signal to a first “off” voltage in response to the carry signal of the subsequent stage,
- wherein N is a positive integer.
10 more elements
Dependencies are inferred from the claim text.