Efficient power transfer power amplifier (PA) architecture

An efficient power transfer power amplifier (PA) architecture comprising:

• a first PA;
• a first impedance transformation network (ITN) having an input coupled to an output of the first PA;
• a second PA;
• a second ITN having an input coupled to an output of the second PA;
• a switching network comprising;
• a plurality of load outputs;
• a first switch input coupled to a first impedance output of the first ITN;
• a second switch input coupled to a second impedance output of the first ITN;
• a third switch input coupled to a third impedance output of the second ITN;
• and
• a fourth switch input coupled to a fourth impedance output of the second ITN;
• and
• a control system adapted to control the switching network in response to a selected mode to switch signals arriving at the first switch input, the second switch input, the third switch input, and the fourth switch input such that select ones of the signals travel paths having matching impedances to loads coupled to select ones of the plurality of load outputs.