CMOS cascode power cells

A method, comprising:

• forming a first complementary oxide semiconductor (“CMOS”) device configured to form a gain stage of a power amplifier, including the steps of:
• doping a first area in an upper surface of a semiconductor substrate with a dopant of a first type to form a first well of a first type in the upper surface of the semiconductor substrate,
• doping a first region and a second region in an upper surface of the first well of the first type with a dopant of a second type to form a first drain region and a first source region that are laterally spaced from each other, and
• forming a first gate structure above the upper surface of the first well of the first type;
• and
• forming a second complementary oxide semiconductor (“CMOS”) device configured to form a voltage buffer stage of the power amplifier, including the steps of:
• doping a second area in the upper surface of the semiconductor substrate with a dopant of the second type to form a first well of the second type in the upper surface of the semiconductor substrate adjacent to the first well of the first type,
• doping at least one third region in an upper surface of the first well of the second type with a dopant of the second type to form a second drain region and a second source region that are laterally spaced from each other, and
• forming a second gate structure above the upper surface of the first well of the second type;
• and
• coupling the second source region to the first drain region to form the power amplifier.

A power amplifier, comprising:

• an enhancement NMOS transistor configured to form a gain stage of the power amplifier, the enhancement NMOS transistor including:
• a first doped well of a first type formed in an upper surface of a semiconductor substrate,
• a first drain region and a first source region spaced laterally from one another in an upper surface of the first doped well, and
• a first gate structure formed over a first channel region defined between the first drain region and the first source region in the first doped well of the first type;
• and
• a CMOS device configured to form a voltage buffer stage of the power amplifier, the CMOS device including:
• a first doped well of a second type formed in an upper surface of the semiconductor substrate such that the first doped well of the second type is disposed adjacent to the first doped well of the first type,
• a second drain region and a second source region spaced laterally from one another in an upper surface of the first doped well of the first type, and
• a second gate structure formed over a second channel region defined between the second drain region and the second source region in the first doped well of the second type,
• wherein the second source region is coupled to the first drain region.