Driving circuit and error amplifier thereof

A driving circuit comprising:

• an inductor electrically connected between a voltage supply and an operative node;
• a driving transistor electrically connected to the operative node;
• an error amplifier electrically connected to a compensation capacitor, the error amplifier comprising:
• an input stage configured to provide a first differential output signal and a second differential output signal in response to a comparison between a fixed reference voltage and a varying feedback voltage;
• a main output stage configured to charge the compensation capacitor;
• and
• an auxiliary output stage configured to be activated to charge the compensation capacitor, wherein in a first operation, both the main output stage and the auxiliary output stage charge the compensation capacitor, and in a second operation, the main output stage charges the compensation capacitor and the auxiliary output stage is deactivated and does not charge the compensation capacitor;
• and
• a comparator electrically connected to the compensation capacitor, wherein the comparator is configured to provide a driving voltage to drive the driving transistor in response to a comparison between a ramp voltage and a compare voltage of the compensation capacitor.

An error amplifier comprising:

• an input stage configured to receive reference voltage and a feedback voltage, and to provide a first differential output signal and a second differential output signal in response to a comparison between the reference voltage and the feedback voltage;
• a first transistor electrically connected between a first voltage and a compensation capacitor, having a gate end configured to receive the first differential output signal;
• a second transistor electrically connected between a second voltage and the compensation capacitor, having a gate end configured to receive the second differential output signal;
• a third transistor electrically connected between the first voltage and the compensation capacitor, having a gate end configured to receive the first differential output signal;
• and
• a fourth transistor electrically connected between the second voltage and the compensation capacitor, having a gate end configured to receive the second differential output signal;
• wherein in a first operation, the first transistor, the second transistor, the third transistor, and the fourth transistor are activated to charge the compensation capacitor with a relative high current, and
• wherein in a second operation, the first transistor and the second transistor are activated, and the third transistor and the fourth transistor are deactivated, such that the compensation capacitor is charged with a relative low current.