Method of manufacturing organic light emitting diode display

A method for manufacturing an organic light emitting diode (OLED) display, the method comprising:

• sequentially stacking an impurity-doped first amorphous silicon layer, a gate insulating layer, and an impurity-non-doped second amorphous silicon layer on a substrate;
• forming a first polysilicon layer and a second polysilicon layer by crystallizing the first and the second amorphous silicon layers, respectively;
• forming a first polysilicon layer pattern, a gate insulating layer pattern, and a second polysilicon layer pattern intermediate in the same pattern by patterning the first polysilicon layer, the gate insulating layer, and the second polysilicon layer;
• sequentially stacking an impurity-doped third amorphous silicon layer and a data metal layer on the second polysilicon layer pattern intermediate;
• forming a photosensitive film pattern on the data metal layer, the photosensitive film pattern including a plurality of units with different thicknesses;
• and
• forming a second polysilicon layer pattern, a third amorphous silicon layer pattern, and a data metal layer pattern by patterning the second polysilicon layer pattern intermediate, the third amorphous silicon layer, and the data metal layer through the photosensitive film pattern,
• wherein forming the second polysilicon layer pattern, third amorphous silicon layer pattern, and data metal layer pattern includes:
• forming a second polysilicon layer pattern, a third amorphous silicon layer pattern intermediate, and a data metal layer pattern intermediate by patterning the second polysilicon layer pattern intermediate, the third amorphous silicon layer, and the data metal layer through a first etching process using the photosensitive film pattern, and
• forming a third amorphous silicon layer pattern and a data metal layer pattern by patterning the third amorphous silicon layer pattern intermediate and the data metal layer pattern intermediate through a second etching process using the photosensitive film pattern, and
• wherein:
• the first polysilicon layer pattern includes a first gate electrode, a second gate electrode, and a first capacitor electrode,
• the second polysilicon layer pattern includes a first active layer and a second active layer formed on the first gate electrode and the second gate electrode, respectively, and a capacitor polycrystalline dummy layer formed on the first capacitor electrode,
• the third amorphous silicon layer pattern includes a first source resistant contact layer and a first drain resistant contact layer respectively formed on a region of the first active layer, a second source resistant contact layer and a second drain resistant contact layer formed on a region of the second active layer, a capacitor amorphous dummy layer formed on the capacitor polycrystalline dummy layer, a dummy data line, and a dummy common power line, and
• the data metal layer pattern includes a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode respectively formed on the first source resistant contact layer, the first drain resistant contact layer, the second source resistant contact layer, and the second drain resistant contact layer, a second capacitor electrode formed on the capacitor amorphous dummy layer, a data line formed on the dummy data line, and a common power line formed on the dummy common power, and
• wherein the photosensitive film pattern includes a first thickness unit, a second thickness unit thinner than the second thickness unit, and an opening having no thickness.