Display panel

A display panel, comprising:

• a substrate, having a display region and a peripheral region;
• at least one thin film transistor device, disposed in the display region, wherein the thin film transistor device comprises two doped layers disposed on the substrate;
• a patterned dielectric layer, comprising:
• an inter-layered dielectric (ILD) layer, disposed in the display region and over the thin film transistor device;
• and
• a sealant stage, disposed in the peripheral region and surrounding the display region;
• a patterned metal layer, comprising:
• at least one signal line, disposed on the ILD layer in the display region;
• and
• at least one first connecting line and at least one second connecting line, disposed in the peripheral region, the first connecting line being disposed in an inner side of the sealant stage facing the display region and electrically connected to the signal line, and the second connecting line being disposed in an outer side of the sealant stage opposite to the display region;
• and
• at least one bridge line, disposed in the peripheral region, the bridge line being disposed at least under the sealant stage, wherein the first connecting line and the second connecting line are electrically connected to each other through the bridge line, and the bridge line and the doped layers are made of a same patterned doped layer.

A display panel, comprising:

• a substrate, having a display region and a peripheral region;
• at least one thin film transistor device, disposed in the display region, wherein the thin film transistor device comprises a gate electrode and two first doped layers disposed on the substrate;
• a patterned dielectric layer, comprising:
• an inter-layered dielectric (ILD) layer, disposed in the display region and over the thin film transistor device;
• and
• a sealant stage, disposed in the peripheral region and surrounding the display region;
• a first patterned metal layer, comprising:
• at least one signal line, disposed on the ILD layer in the display region;
• and
• at least one first connecting line and at least one second connecting line, disposed in the peripheral region, the first connecting line being disposed in an inner side of the sealant stage facing the display region and electrically connected to the signal line, and the second connecting line being disposed in an outer side of the sealant stage opposite to the display region;
• and
• at least one bridge line, disposed in the peripheral region, the bridge line being disposed at least under the sealant stage, wherein the first connecting line and the second connecting line are electrically connected to each other through the bridge line, the bridge line is a composite-layered bridge line formed by stacking a second doped layer with a second patterned metal layer, and the second patterned metal layer and the gate electrode are formed by a same metal layer.

A display panel, comprising:

• a substrate, having a display region and a peripheral region;
• at least one thin film transistor device, disposed in the display region;
• a patterned dielectric layer, comprising:
• an inter-layered dielectric (ILD) layer, disposed in the display region and over the thin film transistor device;
• and
• a sealant stage, disposed in the peripheral region and surrounding the display region;
• a patterned metal layer, comprising:
• at least one signal line, disposed on the ILD layer in the display region;
• and
• at least one first connecting line and at least one second connecting line, disposed in the peripheral region, the first connecting line being disposed in an inner side of the sealant stage facing the display region and electrically connected to the signal line, and the second connecting line being disposed in an outer side of the sealant stage opposite to the display region;
• at least one bridge line, disposed in the peripheral region, the bridge line being disposed at least under the sealant stage, wherein the first connecting line and the second connecting line are electrically connected to each other through the bridge line;
• an encapsulation substrate, disposed opposite to the substrate;
• and
• a sealant disposed between the sealant stage and the encapsulation substrate, wherein the sealant does not overlap the first connecting line and the second connecting line in a vertical projection direction.