Method for manufacturing three-dimensional semiconductor memory device

#This application is a National Phase application of, and claims priority to, PCT Application No. PCT/CN2011/076695, filed on Jun. 30, 2011, entitled “METHOD FOR MANUFACTURING THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE”, which claimed priority to Chinese Application No. 201010611894.X, filed on Dec. 29, 2010. Both the PCT Application and Chinese Application are incorporated herein by reference in their entireties.

#The present disclosure relates to the field of microelectronics technology, and in particular, to a method for manufacturing a three-dimensional semiconductor memory device.

#Semiconductor storage technology is one of key technologies in the field of microelectronics technology. As focus of information technology turns from networks and computers to storage, research of storage technology becomes an important direction of information technology research. Current research of storage technology mainly focuses on high-density and high-performance non-volatile flash technology. As device sizes continuously decrease, conventional FLASH technology encounters great difficulties during size scaling, such as crosstalk and low writing speed, etc. As a result, the conventional FLASH technology cannot satisfy requirements of storage technology development of post-20 nm-node. New storage technology is required for high-capacity storage.

#FIG. 1 shows a cross-sectional view along a bit-line direction of a 1T1R-type three-dimensional memory structure proposed by the applicant;

#FIG. 2 shows a cross-sectional view along a word-line direction of a 1T1R-type three-dimensional memory structure proposed by the applicant;

#FIG. 3 shows a comparison between a whole stack height obtained when a via has a top diameter of 100 nm, a bottom diameter of 30 nm, and an etching angle of 85 degree and a whole stack height obtained when a via has a top diameter of 100 nm, a bottom diameter of 0 nm, and an etching angle of 85 degree;

#Next, the present disclosure will be more specifically explained in connection with specific embodiments and with reference to the drawings, whereby objects, solutions, and advantages of the present disclosure will become more apparent.

#The present disclosure provides a method for manufacturing a three-dimensional semiconductor memory device, comprising: step A: forming an access transistor on a substrate; step B: forming a first storage sub-array comprising a plurality of vertical ring-shape resistive cells on the access transistor, comprising: step B1: depositing a plurality of isolation layers and a plurality of sacrificing layers, alternatively; step B2: etching a via to define a bottom electrode region of the vertical ring-shape resistive cells, the bottom electrode region being connected downward with a drain of the access transistor; step B3: depositing a bottom electrode of the first storage sub-array in the via; and step B4: depositing an insulation dielectric layer; step C: forming a second storage sub-array comprising a plurality of vertical ring-shape resistive cells on the first storage sub-array, comprising: step C1: depositing a plurality of isolation layers and a plurality of sacrificing layers; step C2: etching a via to define a bottom electrode region, which extends downward to the bottom electrode of the first storage sub-array; step C3: depositing a bottom electrode of the second storage sub-array in the via, wherein the bottom electrode of the second storage sub-array is connected with the bottom electrode of the first storage sub-array; and step C4: depositing an insulation dielectric layer.

#The method may further comprise, after the step C: repeating the step C to form an Nth storage sub-array on an (N−1)th storage sub-array. The method may further comprise, before the step B: determining a number of layers of the vertical ring-shape resistive cells based on a ratio between depth and diameter of the via and a height of each vertical ring-shape resistive cell; and determining a number of the sacrificing layers based on the number of layers of the vertical ring-shape resistive cells.