High-k / metal gate CMOS transistors with TiN gates

A process of forming an integrated circuit with replacement metal gate CMOS transistors, comprising the steps:

• providing a partially processed integrated circuit with a PMOS transistor with a first polysilicon gate on a first gate dielectric and an NMOS transistor with a second polysilicon gate on a second gate dielectric and with premetal dielectric that overlies the NMOS and PMOS transistors and wherein the premetal dielectric is planarized exposing the top surface of the first and second polysilicon gates;
• etching to remove the first and second polysilicon gates from first and second gate dielectric to form a PMOS and an NMOS replacement gate transistor trench;
• depositing a first high-k dielectric in the PMOS replacement gate transistor trench;
• depositing at least 8 nm of PMOS TiN metal gate material on the first high-k dielectric in the PMOS replacement gate transistor trench and on a second high-k dielectric in the NMOS replacement gate trench;
• annealing the PMOS metal gate material in oxygen to raise the work function to greater than 4.85 eV
• forming an NMOS metal gate pattern with an opening over the NMOS replacement gate transistor trench;
• etching the PMOS metal gate material from the NMOS replacement gate transistor trench to remove it from an underlying dielectric;
• removing the NMOS metal gate pattern;
• depositing second high-k dialectic in the NMOS replacement gate transistor trench;
• depositing between about 1 nm and 3 nm NMOS TiN metal gate material with a reduced oxygen concentration and a work function of less than about 4.25 eV on the second high-k dielectric;
• depositing a filler metal over the NMOS TiN metal gate material to overfill the PMOS replacement gate transistor trench and to overfill the NMOS replacement gate transistor trench;
• and
• polishing to remove the overfill, and portions of the PMOS TiN metal gate material and the NMOS TiN metal gate material from the surface of the premetal dielectric.

A process of forming an integrated circuit with metal gate first CMOS transistors, comprising the steps:

• providing a partially processed integrated circuit with shallow trench isolation separating a first region with a first sacrificial dielectric where a PMOS metal gate transistor is to be formed from a second region with a second sacrificial dielectric where an NMOS metal gate transistor is to be formed;
• depositing a first high-k dielectric where the PMOS metal gate transistor is to be formed;
• depositing at least 8 nm of PMOS TiN metal gate material on the first high-k dielectric;
• annealing the PMOS metal gate material in oxygen to raise the work function to greater than 4.85 eV
• forming an NMOS metal gate pattern on the PMOS metal gate material with an opening where the NMOS metal gate transistor is to be formed;
• etching the PMOS TiN metal gate material to remove it from an underlying dielectric;
• depositing second high-k dielectric where the NMOS metal gate transistor is to be formed;
• depositing between 1 nm and 3 nm NMOS TiN metal gate material with a reduced oxygen concentration and with a work function of less than 4.25 eV;
• depositing polysilicon over the NMOS TiN metal gate material;
• forming a transistor gate pattern on the polysilicon with resist geometries where gates of the NMOS and PMOS transistor gates are to be formed;
• and
• etching the polysilicon and the PMOS TiN metal gate material to form the PMOS transistor gate;
• and
• etching the polysilicon and the NMOS TiN metal gate material to form the NMOS transistor gate.