US 9,070,770 B2Granted

Low interfacial defect field effect transistor

AssigneeInternational Business Machines Corporation

InventorsAnirban Basu, Guy Cohen, Amlan Majumdar

Life of this patent

Estimating the term…

Loading patent…

Abstract

A disposable gate structure straddling a semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask. A planarization dielectric layer is formed such that a top surface of the planarization dielectric layer is coplanar with the disposable gate structure. A gate cavity is formed by removing the disposable gate structure. An epitaxial cap layer is deposited on physically exposed semiconductor surfaces of the semiconductor fin by selective epitaxy. A gate dielectric layer is formed on the epitaxial cap layer, and a gate electrode can be formed by filling the gate cavity. The epitaxial cap layer can include a material that reduces the density of interfacial defects at an interface with the gate dielectric layer.

Claims15

Dependent claims

A semiconductor structure comprising:

a semiconductor fin comprising a first semiconductor material, said semiconductor fin comprising a source region located on a source-side buffer material portion that is in contact with a portion of a substrate, a drain region located on a drain-side buffer material portion that is in contact with another portion of said substrate, and a body region laterally contacting said source region and said drain region and vertically spaced from said substrate;
and
a cap layer comprising a second semiconductor material and contacting a top surface, a bottom surface and a pair of sidewalls of said body region, a sidewall of said source-side buffer material region and a sidewall of said drain-side buffer material region, wherein a horizontal interface between said source region and said source-side buffer material portion, a horizontal interface between said drain region, and said drain-side buffer material portion and a horizontal interface between said bottom surface of said body region and said cap layer are within a same horizontal plane.

Dependencies are inferred from the claim text.

Facts

Application: 14/010,585Filed 27 Aug 2013
Published: US 2015/0061013 A15 Mar 2015
Granted: 30 Jun 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10D 64/512
For igfets: disposition of the gate electrodes, e.g. buried gates
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 30/6735
Characterised by the shapes, relative sizes or dispositions of the gate electrodes: having gates fully surrounding the channels, e.g. gate-all-around