Semiconductor device with a depletion channel and method of manufacturing the same

A method of manufacturing a semiconductor device, comprising:

• forming a depletion-type channel region by introducing an impurity of a first conductivity type into a region in a surface portion of a semiconductor substrate of a second conductivity type;
• forming a gate insulating film and a gate electrode film on an upper surface of the semiconductor substrate;
• processing the gate electrode film, the gate insulating film, and the semiconductor substrate forming an element isolating trench in an outer region which is spaced apart from a periphery of the channel region;
• introducing an impurity of the second conductivity type into the element isolating trench forming an impurity region along a wall surface of the semiconductor substrate, the wall surface facing the element isolating trench;
• embedding an insulating film in the element isolating trench forming an element isolation insulating film;
• processing the gate electrode film in such a manner as to form a gate electrode;
• introducing an impurity of the first conductivity type into the channel region on both sides of the gate electrode forming source/drain regions;
• and
• wherein the gate electrode film, the gate insulating film, and the semiconductor substrate are processed in such a manner that D/W is equal to or more than 0.01 or 1% when the ratio D/W is expressed in percentage, where W is a distance of a portion of the element formation region over which the gate electrode traverses, and D is a distance between the channel region and the element isolation insulating film.

A method of manufacturing a semiconductor device comprising:

• forming a CMP stopper film on an upper surface of a semiconductor substrate;
• forming an element isolating trench in a surface portion of the semiconductor substrate in such a manner that an element formation region is left;
• introducing an impurity of a second conductivity type into the element isolating trench forming an impurity region along a wall surface of the semiconductor substrate, the wall surface facing the element isolating trench;
• embedding an insulating film in the element isolating trench forming an element isolation insulating film;
• introducing an impurity of a first conductivity type into an inner region which is in the element formation region of the semiconductor substrate and is spaced apart from a periphery of the element isolation insulating film forming a depletion-type channel region;
• forming a gate insulating film and a gate electrode film in order on the upper surface of the semiconductor substrate;
• processing the gate electrode film forming a gate electrode;
• introducing an impurity of the first conductivity type into the channel region on both sides of the gate electrode forming source/drain regions;
• and
• wherein the impurity of the first conductivity type is introduced into the element formation region of the semiconductor substrate in such a manner that D/W is equal to or more than 0.01 or 1% when the ratio D/W is expressed in percentage, where W is a distance of a portion of the element formation region over which the gate electrode traverses, and D is a distance between the channel region and the element isolation insulating film.