Vertical memory devices and apparatuses

Abstract

Vertical memory devices comprise vertical transistors, buried digit lines extending in a first direction in an array region, and word lines extending in a second direction different from the first direction. Portions of the word lines in a word line end region have a first vertical length greater than a second vertical length of portions of the word lines in the array region. Apparatuses including vertical transistors in an array region, buried digit lines extending in a first direction, and word lines are also disclosed. Each of the word lines extends in a second direction perpendicular to the first direction, is formed over at least a portion of a sidewall of at least some of the vertical transistors, and vertically has a depth in a word line end region about equal to or greater than a depth thereof in the array region.

Dependencies are inferred from the claim text.