Semiconductor device layout structure
AssigneeVanguard International Semiconductor Corporation
InventorsRudy Octavius Sihombing, Shang-Hui Tu
Life of this patent
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Abstract
A semiconductor device layout structure is provided. The semiconductor device layout structure includes an active region having a first conductivity type over a semiconductor substrate. The active region is provided with semiconductor devices formed thereon. A first super junction layout unit in the active region includes a first trench. A first doped region having a first conductivity type is formed surrounding the first trench. A second trench is formed surrounding the first doped region. A second doped region having a second conductivity type is formed surrounding the second trench. The first trench is laterally separated from the second trench through the first doped region and the second doped region in a plan view.
Claims40
A semiconductor device layout structure, comprising:
- an active region having a first conductivity type over a semiconductor substrate, wherein the active region is provided with semiconductor devices formed thereon;
- and
- a first super junction layout unit in the active region, comprising:
- a first trench;
- a first doped region having a first conductivity type, surrounding the first trench;
- a second trench surrounding the first doped region;
- and
- a second doped region having a second conductivity type, surrounding the second trench, wherein the first trench is laterally separated from the second trench through the first doped region and the second doped region in a plan view.
A semiconductor device layout structure, comprising:
- an active region having a first conductivity type over a semiconductor substrate, wherein the active region is provided with semiconductor devices formed thereon;
- and
- a super junction layout unit in the active region, comprising:
- a first trench having a first sidewall and a second sidewall adjacent to the first sidewall;
- a first doped region having a first conductivity type, surrounding the first trench;
- a second trench close to the first sidewall of the first trench;
- a second doped region having a second conductivity type, surrounding the second trench, wherein the first trench is laterally separated from the second trench through the first doped region and the second doped region in a plan view;
- a third trench close to the second sidewall of the first trench;
- and
- a third doped region having the second conductivity type, surrounding the second trench, wherein the first trench is laterally separated from the third trench through the first doped region and the third doped region in a plan view.
A semiconductor device layout structure, comprising:
- an active region having a first conductivity type over a semiconductor substrate, wherein the active region is provided with semiconductor devices formed thereon;
- and
- a super junction layout unit in the active region, comprising:
- a first trench;
- a first doped region having a first conductivity type, surrounding the first trench;
- a second trench close to the first trench;
- a second doped region having a second conductivity type, surrounding the second trench, wherein the first trench is laterally separated from the second trench through the first doped region and the second doped region in a plan view, and wherein a first sidewall of the first trench and a second sidewall of the second trench close to the first sidewall are parallel to each other.
Dependencies are inferred from the claim text.