Semiconductor devices having through-vias and methods for fabricating the same

A method of forming a semiconductor device, comprising:

• providing a conductive via extending in a vertical direction through a substrate, a first end of the conductive via extending through a first surface of the substrate, so that the first end projects in a vertical direction relative to the first surface of the substrate;
• providing an insulating layer on the first end of the conductive via and on the first surface of the substrate;
• providing a mask layer on the insulating layer, and patterning the mask layer to form a mask layer pattern, the mask layer pattern having an opening at a side of the conductive via;
• removing an upper portion of the mask layer pattern so that a capping portion of the insulating layer that is on the first end of the conductive via is exposed;
• and
• removing a portion of the insulating layer at a side of, and spaced apart from, the conductive via, using the mask layer pattern as an etch mask, to form an alignment key opening in the insulating layer;
• and
• following forming the alignment key opening, planarizing the first end of the conductive via.

A method for fabricating a semiconductor device, the method comprising:

• forming a through-via that penetrates a substrate, the through-via including a bottom end that protrudes outward from a bottom surface of the substrate;
• forming a lower insulation layer on the bottom surface of the substrate;
• patterning the lower insulation layer to remove a capping part thereof that covers the bottom end of the through-via such that the lower insulation layer remains along sidewalls of the through-via extending to the bottom end of the through-via;
• forming an alignment key that is defined at a recessed portion of the lower insulation layer simultaneously with the removal of the capping part;
• planarizing the bottom surface of the substrate to expose the bottom end of the through-via, and
• after forming the lower insulation layer, further comprising:
• forming a mask layer on the lower insulation layer;
• patterning the mask layer to form an opening configured to expose a portion of the lower insulation layer, the exposed portion of the lower insulation layer being defined as the alignment key;
• and
• recessing the mask layer to expose the capping part of the lower insulation layer,
• wherein the patterning of the lower insulation layer is performed by an etching process that uses the recessed mask layer as an etching mask.