Electroplating using dielectric bridges

#At least some embodiments disclosed herein generally relate to a structure and method for semiconductor devices, and more particularly, but not limited to, a dielectric bridge structure and method for wafer-level chip-scale devices and flip-chip devices.

#Additive electroplating processes on targeted areas of the surface of a semiconductor device are established bumping technologies in the semiconductor industry. Two primary components for electroplating targeted areas on the surface of a semiconductor device include a deposited conductive metal seed layer (which can be comprised of one, two or more stacked layers of deposited metal) that provides an electrically continuous current pathway to the targeted areas of the device, and a masking-type resist material on top of the metal seed layer that defines the areas targeted for plating by covering the areas where additive plating is not desired.

#The use of additive electroplating bumping technologies has oftentimes been frustrated by the absence of plating occurring in all targeted locations or with locations having severely uneven plating. Subsequent analysis has routinely determined that the deposited metal seed layer had been discontinuous due to the topography of wafer features. The most predominant type of topographical issue causing discontinuity or break in the metal seed layer is an adverse sidewall profile of a dielectric layer(s) or a slightly lifted dielectric layer(s) at the dielectric edges beneath the deposited seed layer.

#The embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.

#FIG. 1 illustrates a semiconductor wafer 8 having dicing street areas 202 separating a plurality of die. Wafer 8 has been coated with a metal seed layer (described in more detail below). Electrical current contacts 10 are located around the perimeter at the edge of wafer 8 for applying an electric current in an additive electroplating process as described below.

#FIG. 2 illustrates four dielectric bridges 106 over dicing street areas 202 allowing a metal seed layer to electrically connect a first die 101 to four adjacent die during an electroplating process, according to one embodiment.

#The following description and drawings are illustrative and are not to be construed as limiting. Numerous specific details are described to provide a thorough understanding. However, in certain instances, well known or conventional details are not described in order to avoid obscuring the description. References to one or an embodiment in the present disclosure are not necessarily references to the same embodiment; and, such references mean at least one.

#Reference in this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others. Similarly, various requirements are described which may be requirements for some embodiments but not other embodiments.

#Typically, dicing street areas are kept clear of certain dielectric layers to avoid complications from saw tool wear and residual defects. As such, these particular dielectric layers are usually terminated at or near each die edge on a semiconductor wafer during processing. Some dielectric layers are terminated away from the die edge.