Memory unit, memory unit array and method of manufacturing the same

A memory unit array comprising:

• a substrate having a plurality of active areas;
• a plurality of first word lines and second word lines, wherein the first word lines correspondingly pass through the active areas, and the second word lines correspondingly pass through the intervals between the immediately adjacent active areas;
• a plurality of bit lines;
• a plurality of memory units formed in the substrate, and arranged into a plurality of rows and a plurality of columns, wherein the memory units are respectively disposed in the active areas of the substrate and each memory unit includes
• at least one first recessed access element extending into the substrate for connecting one of the memory units to one of the corresponding first word line, wherein the first recessed access element has a recessed access transistor having a first recessed gate structure extending into the substrate and electrically connected to the corresponding first word line;
• and
• at least one charge storage element electrically connected to the first recessed access element, wherein the charge storage element is electrically connected to one of the bit lines through the first recessed access element;
• and
• a plurality of isolation portions extending into the substrate and correspondingly adjacent to the active areas, wherein each isolation portion includes a trenched isolating barrier and a second recessed access element, wherein the second recessed access element is disposed in the trenched isolating barrier, the trenched isolating barrier provides electrical insulation between the second recessed access element and the corresponding charge storage unit, and the second recessed access element is electrically connected to the corresponding second word line.

A method of manufacturing memory unit array comprising:

• forming a plurality of memory units in a substrate, the memory units being respectively disposed in a plurality of active areas of the substrate, wherein each memory unit includes a first recessed access element and a charge storage element electrically connected to the first recessed access element, wherein the first recessed access element is a recessed access transistor having a first recessed gate structure extending into the substrate;
• and
• forming a plurality of isolation portions in the substrate correspondingly adjacent to the memory units for isolating the memory units,
• wherein each of the isolation portions extends into the substrate and each of the isolation portions includes a trenched isolating barrier and a second recessed access element, wherein the second recessed access element is disposed in the trenched isolating barrier, and the trenched isolating barrier provides electrical insulation between the second recessed access element and the charge storage element of the correspondingly memory unit.