Lateral power semiconductor transistors

A method of increasing switching speed of a lateral power semiconductor transistor, the transistor comprising:

• a contact region of a first conductivity type located within a first semiconductor region of a second, opposite conductivity type;
• a source region of the second conductivity type located within a second semiconductor region of the first conductivity type;
• a lateral drift region of the second conductivity type placed between the first semiconductor region and the second semiconductor region, the lateral drift region to be depleted of mobile carriers at breakdown voltage during an off-state blocking mode of the transistor and able to conduct charge during an on-state conducting mode of the transistor;
• and
• a gate placed above the second semiconductor region, the gate to control charge in a channel region between the lateral drift region and the source region of the second conductivity type and to thereby control flow of charge within the lateral drift region;
• the method comprising:
• forming a first floating semiconductor region of the first conductivity type within the first semiconductor region, the first floating semiconductor region being located laterally spaced to the contact region and having a higher doping concentration than the first semiconductor region of the second conductivity type;
• forming a second floating semiconductor region of the second conductivity type within the first semiconductor region, the second floating semiconductor region being located laterally adjacent the first floating semiconductor region and having a higher doping concentration than the first semiconductor region of the second conductivity type, and
• forming a floating electrode placed above and in direct contact to the first and second floating semiconductor regions.

A lateral bipolar power semiconductor transistor comprising:

• a contact region of a first conductivity type located within a first semiconductor region of a second, opposite conductivity type;
• a source region of the second conductivity type located within a second semiconductor region of the first conductivity type;
• a lateral drift region of the second conductivity type placed between the first semiconductor region and the second semiconductor region, the lateral drift region to be depleted of mobile carriers at breakdown voltage during an off-state blocking mode of the transistor and able to conduct charge during an on-state conducting mode of the transistor;
• a gate placed above the second semiconductor region, the gate to control charge in a channel region between the lateral drift region and the source region of the second conductivity type and to thereby control flow of charge within the lateral drift region;
• at least one floating structure comprising at least two floating semiconductor regions of opposite conductivity types and a floating electrode which is placed above and in direct contact with the at least two floating semiconductor regions, the at least one floating structure being located within the first semiconductor region,
• wherein the contact region is a charge injection region and the floating electrode of the at least one floating structure is configured to remove both electrons and holes to reduce charge injection from the charge injection region.

A lateral bipolar power semiconductor transistor comprising:

• a contact region of a first conductivity type located within a first semiconductor region of the first conductivity type;
• a second contact region of a second, opposite conductivity type located within a second semiconductor region of the second conductivity type;
• a lateral drift region of the second conductivity type placed between the first semiconductor region and the second semiconductor region, the lateral drift region to be depleted of mobile carriers at breakdown voltage during an off-state blocking mode of the transistor and able to conduct charge during an on-state conducting mode of the transistor;
• wherein at least one of the first and second semiconductor regions comprises:
• a first floating semiconductor region of the first conductivity type within a semiconductor well region and having a higher doping concentration than the semiconductor well region;
• a second floating semiconductor region of the second conductivity type located laterally adjacent the first floating semiconductor region within the semiconductor well region and having a higher doping concentration than the semiconductor well region, and
• a floating electrode placed above and in direct contact to the first and second floating semiconductor regions.