Heterojunction bipolar transistors with reduced parasitic capacitance

A device structure for a heterojunction bipolar transistor, the device structure formed using a semiconductor substrate, the device structure comprising:

• a trench isolation region in the semiconductor substrate;
• a collector in the semiconductor substrate and coextensive with the trench isolation region, the collector having a first width;
• a first semiconductor layer including a section disposed on the collector and on the trench isolation region, the section of the first semiconductor layer comprised of a first single crystal semiconductor material and having a second width greater than the first width;
• a second semiconductor layer including a section disposed on the section of the first semiconductor layer, the section of the second semiconductor layer comprised of a second single crystal semiconductor material, having an outer edge that overlies the trench isolation region, and having a third width greater than the second width;
• and
• a cavity extending laterally beneath the section of the second semiconductor layer from the outer edge of the section of the second semiconductor layer to the section of the first semiconductor layer.