US 9,070,719 B2 · Semiconductor device structure, method for manufacturing the same, and method for manufacturing Fin

Abstract

A semiconductor device structure, a method for manufacturing the same, and a method for manufacturing a semiconductor fin are disclosed. In one embodiment, the method for manufacturing the semiconductor device structure comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction, the second direction crossing the first direction on the semiconductor substrate, and the gate line intersecting the fin with a gate dielectric layer sandwiched between the gate line and the fin; forming a dielectric spacer surrounding the gate line; and performing inter-device electrical isolation at a predetermined position, wherein isolated portions of the gate line form independent gate electrodes of respective devices.

Claims13

Dependent claims

A method for manufacturing a semiconductor device structure, comprising:

forming a fin in a first direction on a semiconductor substrate;
forming a gate line in a second direction, the second direction crossing the first direction on the semiconductor substrate, and the gate line intersecting the fin with a gate dielectric layer sandwiched between the gate line and the fin;
forming a dielectric spacer surrounding the gate line;
and
performing inter-device electrical isolation at a predetermined position after forming the dielectric spacer, wherein isolated portions of the gate line form independent gate electrodes of respective devices.

2 more elements

A semiconductor device structure, comprising:

a semiconductor substrate;
a plurality of devices formed on the semiconductor substrate, each of the devices comprising:
a fin extending in a first direction;
a gate electrode extending in a second direction, the second direction crossing the first direction, and the gate electrode intersecting the fin with a gate dielectric layer sandwiched between the gate electrode and the fin;
and
dielectric spacers on opposite side surfaces of the gate electrode extending in the second direction,
a first electrical isolation at a predetermined position between adjacent devices,
wherein the gate electrodes of respective devices adjacent to each other in the second direction are aligned to each other in the second direction, and the dielectric spacers of the respective devices adjacent to each other in the second direction are aligned to each other in the second direction;
and
end surfaces of the dielectric spacers on the side surfaces of a first device, facing a second device adjacent to the first device in the second direction, are substantially flush with an end surface of the gate electrode of the first device facing the second device;
and
wherein adjacent gate electrodes in the second direction are formed from one gate line extending in the second direction, and the first electrical isolation comprises an insulating material converted from a portion of the gate line at the predetermined position.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/577,942Filed 18 Nov 2011

Priority

CN 2011 1 024093122 Aug 2011

Published

US 2013/0062708 A114 Mar 2013

Granted

30 Jun 2015

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 62/115
Isolations within a component, i.e. internal isolations: dielectric isolations, e.g. air gaps
H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…

Semiconductor device structure, method for manufacturing the same, and method for manufacturing Fin

Life of this patent

Semiconductor device structure, method for manufacturing the same, and method for manufacturing Fin

Life of this patent

Abstract

Claims13