Method for producing a field effect transistor with implantation through the spacers

A method for producing a field effect transistor comprising successively:

• providing a substrate successively comprising a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern,
• covering the semiconductor material layer and the gate pattern by a covering layer,
• implanting a first doping impurity in the semiconductor material layer through the covering layer so as to place a maximum concentration of implanted first doping impurity at a first implantation depth in the semiconductor material layer, and
• partly eliminating the covering layer so as to form lateral spacers leaving source/drain electrodes free,
• wherein implantation is performed in an implantation equipment having a larger first implantation depth than the thickness of the semiconductor material layer.

A method of producing a field effect transistor comprising:

• forming a gate electrode structure on an SOI substrate,
• wherein the SOI substrate includes a support substrate, an insulating layer on the support substrate, and a semiconductor layer on the insulating layer,
• wherein the semiconductor layer includes a channel region under the gate electrode structure, source/drain regions adjacent the channel region,
• wherein the channel region and the source/drain regions of the semiconductor layer have a thickness of smaller than or equal to 8 nm, and
• wherein at least the channel region of the semiconductor layer is fully-depleted silicon and has a single-crystal structure;
• forming a covering layer over the gate electrode structure and the SOI substrate;
• implanting a first dopant impurity in the source/drain regions of the semiconductor layer through the covering layer so as to place a maximum concentration of the implanted first dopant impurity at a first implantation depth from a top surface of the covering layer and located within the source/drain regions of the semiconductor layer,
• wherein the thickness of the semiconductor layer is smaller than the first implantation depth;
• removing the covering layer at least from a portion of the source/drain regions of the semiconductor layer.