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US 9,070,703 B2Granted
High speed digital interconnect and method
AssigneeTexas Instruments Incorporated
InventorsBaher S. Haroun, Marco Corsi, Siraj Akhtar, Nirmal C. Warke
Life of this patent
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Abstract
In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.
Claims22
An apparatus comprising:
- a first packaged integrated circuit (IC) that includes:
- a substrate;
- a first housing having a first receptacle formed therein;
- and
- a first IC that is secured within the first housing and that includes a first directional antenna that is located in proximity to the first receptacle,
- a second packaged IC that includes:
- a second housing having a second receptacle formed therein;
- and
- a second IC that is secured within the second housing and that includes a second directional antenna that is located in proximity to the second receptacle;
- a directional dielectric waveguide that is secured to the first housing in the first receptacle and the second housing in the second receptacle, wherein the directional dielectric waveguide is adapted to provide a sub-millimeter wave radio frequency (RF) link between the first and second directional antennas, and
- a beam steering circuit that is coupled to the first directional antenna, wherein the beam steering circuit changes an electric propagation characteristic of the first directional antenna itself, and wherein the beam steering circuit is contained on or in the first packaged IC;
- wherein the sub-millimeter wave RF link is produced by a high frequency oscillator built on the substrate, wherein the oscillator is constructed by a complementary metal-oxide-semiconductor (CMOS) process technology.
9 more elements
An apparatus comprising:
- a first packaged IC that includes:
- a substrate;
- a first plastic housing having a first receptacle formed therein;
- a first IC that is encapsulated within the first housing and that includes a first directional antenna that is located in proximity to the first receptacle;
- a first leadframe that is at least partially encapsulated within the first plastic housing;
- and
- a first set of wire bonds to secured to the first IC and to the first leadframe, wherein each bond wire from the first set is encapsulated within the first plastic housing;
- a second packaged IC that includes:
- a second plastic housing having a second receptacle formed therein;
- a second IC that is encapsulated within the second housing and that includes a second directional antenna that is located in proximity to the second receptacle;
- a second leadframe that is at least partially encapsulated within the second plastic housing;
- and
- a second set of wire bonds to secured to the second IC and to the second leadframe, wherein each bond wire from the second set is encapsulated within the second plastic housing;
- a directional dielectric waveguide that is secured to the first housing in the first receptacle and the second housing in the second receptacle, and
- a beam steering circuit that is coupled to the directional dielectric waveguide, wherein the beam steering circuit is adapted to adjust the first directional antenna to couple the IC with the directional dielectric waveguide, wherein the beam steering circuit changes an electric propagation characteristic of the first directional antenna itself, and wherein the beam steering circuit is contained on or in the first packaged IC;
- wherein the directional dielectric waveguide is adapted to provide a sub-millimeter wave RF link between the first and second directional antennas, wherein the sub-millimeter wave RF link is produced by a high frequency oscillator built on the substrate, wherein said oscillator is constructed by a complementary metal-oxide-semiconductor (CMOS) process technology.
13 more elements
Dependencies are inferred from the claim text.