Packaged semiconductor chips with array

A method of manufacture of a chip-sized wafer level packaged device comprising:

• attaching a first semiconductor layer to a second semiconductor layer, the first semiconductor layer including at least one device and electrical circuitry including first and second bond pads adjacent to a surface of the first semiconductor layer facing the second semiconductor layer;
• forming a first opening through the second semiconductor layer to at least a portion of the first bond pad;
• forming a first monolithic plated conductor through said first opening and on the at least a portion of the first bond pad;
• and
• forming a second opening through the first semiconductor layer to at least a portion of the second bond pad;
• forming a second monolithic plated conductor through second said opening and on the at least a portion of the second bond pad;
• forming a first compliant layer over said first semiconductor layer and underlying said first monolithic plated conductor;
• forming a second compliant layer over said first semiconductor layer and underlying said second monolithic plated conductor;
• and
• forming a third conductor over said second compliant layer and underlying said second monolithic plated conductor.

A method of manufacture of a chip-sized wafer level packaged device comprising;

• attaching a first semiconductor layer to a second semiconductor layer, the first semiconductor layer including at least one device and electrical circuitry including first and second bond pads adjacent to a surface of the first semiconductor layer facing the second semiconductor layer, wherein said first semiconductor layer includes a material having thermal expansion characteristics similar to those of said device;
• forming a first opening through the second semiconductor layer to at least a portion of the first bond pad;
• forming a first monolithic plated conductor through said first opening and on the at least a portion of the first bond pad;
• forming a second opening through the first semiconductor layer to at least a portion of the second bond pad;
• forming a second monolithic plated conductor through second said opening and on the at least a portion of the second bond pad;
• forming a first compliant layer on said first semiconductor layer and underlying said first monolithic plated conductor;
• and
• forming a second compliant layer on said second semiconductor layer and underlying said second monolithic plated conductor.

A method of manufacture of stacked chip-sized, wafer level packaged devices comprising:

• providing at least first and second chip-sized wafer level packaged devices, wherein each of the first and second packaged devices is manufactured by:
• attaching a first semiconductor layer to a second semiconductor layer, the first semiconductor layer including at least one device and electrical circuitry including first and second bond pads adjacent to a surface of the first semiconductor layer facing the second semiconductor layer;
• forming a first opening through the second semiconductor layer extending to at least a portion of the first bond pad;
• forming a first monolithic plated conductor through said first opening and extending to the at least a portion of the first bond pad at the first opening;
• forming a second opening through the first semiconductor layer to at least a portion of the second bond pad;
• and
• forming a second monolithic plated conductor through second said opening and on the at least a portion of the second bond;
• and
• electrically coupling said first monolithic plated conductor of said first device to said second monolithic plated conductor of said second device.