Semiconductor packages including graphene layers
AssigneeSamsung Electronics Co., Ltd.
InventorSoojeoung Park
Life of this patent
Estimating the term…
Abstract
A semiconductor package comprises a lower package comprising a lower substrate, a lower semiconductor chip on the lower substrate, a lower graphene layer on the lower semiconductor chip, and a lower molding layer between the lower substrate and the lower graphene layer. An upper package is on the lower substrate, the upper package spaced apart from the lower package, the upper package comprising an upper substrate, an upper semiconductor chip, and an upper molding layer. Lower conductive bumps are positioned between the lower substrate and the upper substrate, the lower bumps comprising a ground bump and a signal transmitting bump.
Claims20
A semiconductor package comprising:
- a lower package comprising a lower substrate, a lower semiconductor chip on the lower substrate, a lower graphene layer on the lower semiconductor chip, and a lower molding layer between the lower substrate and the lower graphene layer;
- an upper package on the lower substrate, the upper package spaced apart from the lower package, the upper package comprising an upper substrate, an upper semiconductor chip, and an upper molding layer;
- and
- lower conductive bumps between the lower substrate and the upper substrate, the lower conductive bumps comprising a ground bump and a signal transmitting bump.
A semiconductor package comprising:
- a substrate;
- a semiconductor chip on the substrate;
- conductive bumps laterally surrounding the semiconductor chip on the substrate;
- a graphene layer on the semiconductor chip;
- and
- a molding layer between the substrate and the graphene layer,
- wherein the graphene layer is electrically connected to the conductive bumps.
A semiconductor package comprising:
- a substrate;
- a semiconductor chip on the substrate and electrically connected to the substrate;
- a molding layer on the substrate and at a side of the semiconductor chip;
- a graphene layer directly on the semiconductor chip and on the molding layer opposite the substrate;
- and
- conductive bumps on the substrate and through the molding layer, the conductive bumps in contact with the substrate and the graphene layer to electrically connect the substrate and the graphene layer, the molding layer positioned between the conductive bumps and the semiconductor chip.
Dependencies are inferred from the claim text.