Plating structure for wafer level packages

A method for a semiconductor device, the method comprising:

• forming a patterned seed layer on an exposed bonding pad and passivation layer on a semiconductor die singulated from a semiconductor wafer;
• forming a redistribution layer and a plating structure on the patterned seed layer, wherein the plating structure comprises a plating trace extending to an edge of the die;
• forming a second passivation layer on the redistribution layer and the plating structure;
• and
• forming an under bump metal on an exposed portion of the redistribution layer utilizing the plating structure.

A semiconductor device comprising:

• a semiconductor wafer comprising a plurality of semiconductor die, said semiconductor wafer comprising a plating structure for forming an under bump metal on redistribution layers on the plurality of semiconductor die, wherein the plating structure is a plating process electrode terminal and comprises:
• a plating connection line around a periphery of the semiconductor wafer;
• and
• a plating bar coupling the plating connection line to plating traces on the plurality of semiconductor die, wherein the plating traces are electrically coupled to the redistribution layers on the plurality of semiconductor die.