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US 9,070,668 B2Granted
Pads and pin-outs in three dimensional integrated circuits
OwnerRaminda Udaya Maduraweinventor
Life of this patent
Estimating the term…
Abstract
A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.
Claims20
A semiconductor device, comprising:
- a first layer including a circuit;
- a second layer including a plurality of circuits in a first plurality of locations;
- a third layer including a plurality of pads in a second plurality of locations, wherein the plurality of pads are inaccessible from the first layer;
- and
- a plurality of wire interconnects that are positioned through a first portion of the third layer and through a second portion of the second layer, wherein the circuit is configured to depend on the second layer to operate, wherein the first plurality of locations and the second plurality of locations are configured to be independent of the first layer, and wherein the first layer, the second layer, and the third layer form a stack.
2 more elements
A method, comprising:
- forming a stack comprising a first layer including a circuit, a second layer including a plurality of circuits in a first plurality of locations, a third layer including a plurality of pads in a second plurality of locations, and a plurality of wire interconnects that are positioned through a first portion of the third layer and through a second portion of the second layer, wherein the plurality of pads are inaccessible from the first layer;
- and
- coupling a portion of the plurality of circuits to the plurality of pads, wherein the circuit is configured to depend on the second layer to operate, and wherein the first plurality of locations and the second plurality of locations are configured to be independent of the first layer.
A semiconductor device, comprising:
- a substrate including a plurality of circuits in a first plurality of locations;
- a first layer including a circuit;
- a second layer including a plurality of pads in a second plurality of locations, wherein the plurality of pads are inaccessible from the first layer;
- and
- a plurality of wire interconnects that are positioned through a first portion of the second layer and through a second portion of the substrate, wherein the circuit is configured to depend on the substrate to operate, wherein the first plurality of locations and the second plurality of locations are configured to be independent of the first layer, and wherein the substrate, the first layer, and the second layer form a stack.
2 more elements
Dependencies are inferred from the claim text.