Method of forming fine patterns of semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorByoung-Yong Gwak
Life of this patent
Estimating the term…
Abstract
A method of forming fine patterns includes patterning a hard mask layer and a buffer mask layer sequentially stacked on a lower mask layer to form first openings, forming sacrificial patterns filling the first openings and protruding from a top surface of the buffer mask layer, forming a spacer pattern filling a space between two adjacent sacrificial patterns and having gaps each of which exposes a portion of the buffer mask layer between at least three adjacent sacrificial patterns, etching portions of the buffer mask layer exposed by the gaps of the spacer pattern to form enlarged holes, etching portions of the hard mask layer exposed by the enlarged holes to form second openings, and subsequently etching the lower layer using the hard mask layer as an etch mask.
Claims20
A method of forming fine patterns, the method comprising:
- providing a structure including a lower mask layer, a hard mask layer stacked on the lower mask layer and a buffer mask layer stacked on the hard mask layer;
- patterning the hard mask layer and the buffer mask layer to form first openings therein;
- forming sacrificial patterns filling the first openings, the sacrificial patterns protruding from a top surface of the buffer mask layer;
- forming a spacer pattern filling spaces between sacrificial patterns adjacent to each other, the spacer pattern having gaps therein, and each of the gaps exposing a respective portion of the buffer mask layer located in a central region of a polygon whose vertices coincide with the locations of sacrificial patterns adjacent to each other, respectively;
- etching portions of the buffer mask layer exposed by the gaps of the spacer pattern to form holes therein that expose the hard mask layer;
- etching portions of the hard mask layer exposed by the holes in the buffer mask layer to form second openings in the hard mask layer;
- and subsequently etching the lower mask layer using the hard mask as an etch mask.
A method of forming fine patterns, the method comprising:
- providing a structure including a lower mask layer, a hard mask layer stacked on the lower mask layer and a buffer mask layer stacked on the hard mask layer;
- patterning the hard mask layer and the buffer mask layer to form first openings therein;
- forming sacrificial patterns filling the first openings, the sacrificial patterns protruding from a top surface of the buffer mask layer;
- forming a spacer pattern filling spaces between sacrificial patterns adjacent to each other, the spacer pattern having gaps therein, and each of the gaps exposing a respective portion of the buffer mask layer located in a central region of a polygon whose vertices coincide with the locations of sacrificial patterns adjacent to each other, respectively;
- anisotropically etching the buffer mask layer exposed by the gaps of the spacer pattern to form holes in the buffer mask layer;
- performing an isotropic etching process on the buffer mask layer to enlarge the holes in the buffer mask layer, and wherein the enlarged holes expose the hard mask layer;
- removing the spacer pattern;
- after the spacer pattern is removed, anisotropically etching the hard mask layer exposed by the enlarged holes to form second openings in the hard mask layer;
- and subsequently anisotropically etching the lower mask layer using the hard mask layer as an etch mask.
A method of forming a semiconductor device, the method comprising:
- providing a target structure having a first layer disposed thereon and a second layer disposed on the first layer;
- forming an array of openings through the second layer using photolithography and etching processes;
- forming sacrificial patterns that have the form of pillars and occupy the openings, respectively, and wherein each of the sacrificial patterns has an upper portion protruding above a top surface of the second layer;
- conformally forming a spacer layer on the protruding upper portions of the sacrificial patterns to such a thickness that the spacer layer has a portion spanning the upper portions of the sacrificial patterns and recesses are defined by the conformal spacer layer at locations between the sacrificial patterns as viewed in plan;
- etching the spacer layer to extend the recesses and thereby form gaps that expose the top surface of the second layer, and etching the second layer through the gaps to form holes in the second layer;
- isotropically etching the second layer to enlarge the holes in the second layer;
- etching the target structure using an etch mask comprising the second layer having the enlarged holes to extend the enlarged holes into the target structure;
- and
- forming components of the semiconductor device in the holes in the target structure.
Dependencies are inferred from the claim text.