US 9,070,624 B2Granted

Semiconductor device including polysilicon resistor and metal gate resistor and methods of fabricating thereof

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsJian-Hao Chen, Chia-Yu Lu, Tung-Heng Hsieh, Kuo-Feng Yu, Chin-Shan Hou, Hsien-Chin Lin, Shyue-Shyh Lin

Life of this patent

Estimating the term…

Loading patent…

Abstract

A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. 5, 15, 26). Thus, a subsequent planarization process of the dielectric layer may not contact the first gate structure.

Claims18

Dependent claims

A method, comprising:

forming a polysilicon layer on a semiconductor substrate;
etching the polysilicon layer to form a first region having a first height from a top surface of the semiconductor substrate and a second region having a second height from the top surface of the semiconductor substrate, wherein the second height is less than the first height;
forming a first gate structure on the semiconductor substrate, wherein the first gate structure is formed of the second region of the etched polysilicon layer and is disposed over an isolation region of the substrate;
forming a sacrificial gate structure on the semiconductor substrate adjacent the first gate structure, wherein the sacrificial gate structure is formed using the first region of the etched polysilicon layer and is disposed over an active region of the substrate adjacent the isolation region;
and
forming a dielectric layer overlying the first gate structure and the sacrificial gate structure, wherein the dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness above a top surface of the sacrificial gate structure, wherein the second thickness is less than the first thickness;
after forming the dielectric layer, performing a planarization process on the dielectric layer to expose the top surface of the sacrificial gate structure, wherein after performing the planarization process a portion of the dielectric layer having a third thickness remains above the first gate structure;
after the planarization process, removing the sacrificial gate structure to form a trench;
forming a metal gate structure in the trench;
and
forming a first contact to the first gate structure and forming a second contact to the metal gate structure.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/328,875Filed 16 Dec 2011
Published: US 2013/0157452 A120 Jun 2013
Granted: 30 Jun 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 64/01326
Characterised by the conductor: aspects related to lithography, isolation or planarisation of the conductor
H10D 1/47
Resistors: resistors having no potential barriers
H10D 30/60
Field-effect transistors [FET]: insulated-gate field-effect transistors [IGFET]
H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…